87332I-01 2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator DATA SHEET GENERAL DESCRIPTION FEATURES The 87332I-01 is a high performance 2 Differential-to-2.5V/3.3V One 2 differential 2.5V/3.3V LVPECL / ECL output ECL/LVPECL Clock Generator. The CLK, nCLK pair can accept One CLK, nCLK input pair most standard differential input levels The 87332I-01 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed CLK, nCLK pair can accept the following differential output and part-to-part skew characteristics make the 87332I-01 input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL ideal for those clock distribution applications demanding well de ned Maximum output frequency: 500MHz performance and repeatability. Maximum input frequency: 1GHz Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input Part-to-part skew: 400ps (maximum) Propagation delay: 1.6ns (maximum) LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -2.375V to -3.8V CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT MR 1 8 Vcc Q CLK CLK 2 7 Q 2 nQ nCLK nCLK 3 6 nQ nc 4 5 VEE 87332I-01 MR 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View 87332AMI-01 REVISION C 2/12/15 1 2015 Integrated Device Technology, Inc.87332AMI-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description Master reset. When LOW, outputs are enabled. When HIGH, 1 MR Input Pulldown divider is reset forcing Q output LOW and nQ output HIGH. LVCMOS / LVTTL interface level. 2 CLK Input Pulldown Non-inverting differential clock input. 3 nCLK Input Pullup Inverting differential clock input. 4 nc Unused No connect. 5V Power Negative supply pin. EE 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V Power Positive supply pin. CC NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN CLK MR Q FIGURE 1. TIMING DIAGRAM 2, Differential-to-2.5V/3.3V 2 REVISION C 2/12/15 ECL/LVPECL Clock Generator