Low Phase Noise, Dual 1-to-4, 3.3V, 2.5V 8SLVP2104 LVPECL Output Fanout Buffer Datasheet Description Features The 8SLVP2104I is a high-performance differential dual LVPECL Two 1:4, low skew, low additive jitter LVPECL output pairs fanout buffer. The device is designed for the fanout of high-frequency, Two differential clock input pairs very low additive phase-noise clock and data signals. Differential pairs can accept the following differential input The 8SLVP2104I is characterized to operate from a 3.3V or 2.5V levels: LVDS, LVPECL, CML power supply. Guaranteed output-to-output and part-to-part skew Maximum input clock frequency: 2GHz characteristics make the 8SLVP2104I ideal for those clock distribution applications demanding well-defined performance and Output skew: 8ps (typical) repeatability. Two selectable differential inputs and four low skew Propagation delay: 270ps (maximum) outputs are available. The integrated bias voltage reference enable Low additive phase jitter, RMS: 47fs (maximum) easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive Full 3.3V and 2.5V supply voltage phase noise. Maximum device current consumption (I ): 93mA (maximum) EE Available in lead-free (RoHS 6), 28-Lead VFQFN package -40C to 85C ambient operating temperature Supports case temperature 105C operations Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also accept single-ended LVCMOS levels. See Applications section Wiring the Differential Input Levels to Accept Single-ended Levels (Figure 1A and Figure 1B). Block Diagram Pin Assignments QA0 nQA0 21 20 19 18 17 16 15 V CC QB0 22 14 VEE QA1 nQA1 nQB0 23 13 nQA0 PCLKA 24 QB1 12 QA0 nPCLKA QA2 nQB1 25 VREFA 11 nQA2 26 10 nPCLKA QB2 QA3 nQB2 27 PCLKA 9 nQA3 Voltage VCC 28 8 VCC V REFA Reference 12 3 4 5 6 7 QB0 nQB0 V CC QB1 8SLVP2104I nQB1 PCLKB 28-VFQFN nPCLKB QB2 5mm x 5mm x 0.75mm package body nQB2 NB Package QB3 Top View nQB3 Voltage V REFB Reference 2019 Integrated Device Technology, Inc. 1 January 15, 2019 nQA3 VEE QB3 QA3 nQB3 nQA2 nc QA2 PCLKB nQA1 nPCLKB QA1 VCC VREFB8SLVP2104 Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 14 V Power Negative supply pins. EE 2, 3 QB3, nQB3 Output Differential output pair B3. LVPECL interface levels. 4 nc Unused Do not connect. 5 PCLKB Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ Inverting differential LVPECL clock/data input. V /2 default when left CC 6 nPCLKB Input Pulldown floating. 7V Output Bias voltage reference for the PCLKB, nPCLKB input pair. REFB 8, 15, 28 V Power Power supply pins. CC 9 PCLKA Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ Inverting differential LVPECL clock/data input. V /2 default when left CC 10 nPCLKA Input Pulldown floating. 11 V Output Bias voltage reference for the PCLKA, nPCLKA input pair. REFA 12, 13 QA0, nQA0 Output Differential output pair A0. LVPECL interface levels. 16, 17 QA1, nQA1 Output Differential output pair A1. LVPECL interface levels. 18, 19 QA2, nQA2 Output Differential output pair A2. LVPECL interface levels. 20, 21 QA3, nQA3 Output Differential output pair A3. LVPECL interface levels. 22, 23 QB0, nQB0 Output Differential output pair B0. LVPECL interface levels. 24, 25 QB1, nQB1 Output Differential output pair B1. LVPECL interface levels. 26, 27 QB2, nQB2 Output Differential output pair B2. LVPECL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP 2019 Integrated Device Technology, Inc. 2 January 15, 2019