1:18, Low Skew, Low Additive Jitter 8SLVS1118 LVDS/ LVPECL Fanout Buffer Datasheet Description Features The 8SLVS1118 is a high-performance, low-power, differential 1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer 1:18 output fanout buffer. This highly versatile device is designed Low power consumption for the fanout of high-frequency, very low additive phase-noise Differential PCLK, nPCLK clock pair accepts the following clock and data signals. Guaranteed output-to-output and differential/single-ended input levels: LVDS, LVPECL, and part-to-part skew characteristics make the 8SLVS1118 ideal for LVCMOS clock distribution applications that demand well-defined Maximum input clock frequency: 2GHz performance and repeatability. Propagation delay: 290ps (typical) The device is characterized to operate from a 2.5V or 3.3V power Output skew: 40ps (typical) supply. The integrated bias voltage references enable easy Low additive phase jitter, RMS: 39fs (typical), interfacing AC-coupled signals to the device inputs. Integration Range: 12kHz 20MHz, (f 156.25MHz, V 1V, V 3.3V) REF PP DD Full 2.5V and 3.3V supply voltage modes Device current consumption: 180mA (typical) IEE for LVPECL output mode, 400mA (typical) IDD for LVDS output mode 48-VFQFPN, lead-free (RoHS 6) packaging Transistor count: 1762 -40C to +85C ambient operating temperature Supports case temperature up to 105C Block Diagram Q0 8SLV1118I nQ0 Q1 nQ1 Q2 nQ2 51k Pull-down . PCLK . nPCLK Pull-up / . Pull-down 51k 51k Q17 nQ17 Voltage VREF Reference Pull-down SEL LVDS 51k 2019 Integrated Device Technology, Inc. 1 January 15, 20198SLVS1118 Datasheet Pin Assignment Figure 1. Pin Assignment for 7mm 7mm VFQFPN Package Top View 48 47 46 45 44 43 42 41 40 39 38 37 1 nQ10 GND 36 2 35 Q10 Q16 3 34 nQ9 nQ16 4 33 Q9 Q17 5 32 nQ8 nQ17 6 31 Q8 V DD 8SLVS1118 7 30 nQ7 V DD IN 8 29 Q7 VREF 9 28 nQ6 nPCLK 10 27 Q6 PCLK 11 26 nQ5 SEL LVDS 25 GND 12 Q5 13 14 15 16 17 18 19 20 21 22 23 24 Pin Descriptions a Table 1. Pin Descriptions Number Name Type Description 1 GND Power Ground supply pin. 2 Q16 Output Differential output pair. LVPECL/ LVDS interface levels. 3 nQ16 Output Differential output pair. LVPECL/ LVDS interface levels. 4 Q17 Output Differential output pair. LVPECL/ LVDS interface levels. 5 nQ17 Output Differential output pair. LVPECL/ LVDS interface levels. 6V Power Output power supply pin. DD 7V Power Power supply pin. DD IN 8 VREF Output Bias voltage reference for the PCLK, nPCLK input pair. 9 nPCLK Input PD/PU Inverting differential clock/data input. 10 PCLK Input PD Non-inverting differential clock/data input. 11 SEL LVDS Input PD Control input. Output amplitude select for differential outputs. 12 GND Power Power supply ground. 13 V Power Output power supply pin. DD 14 Q0 Output Differential output pair. LVPECL/ LVDS interface levels. 15 nQ0 Output Differential output pair. LVPECL/ LVDS interface levels. 16 Q1 Output Differential output pair. LVPECL/ LVDS interface levels. 2019 Integrated Device Technology, Inc. 2 January 15, 2019 V V DD DD Q0 nQ15 nQ0 Q15 Q1 nQ14 nQ1 Q14 Q2 nQ13 nQ2 Q13 Q3 nQ12 nQ3 Q12 Q4 nQ11 nQ4 Q11 V V DD DD