Crystal or Differential to 8T39S06A Differential Clock Fanout Buffer Datasheet General Description Features The 8T39S06A is a high-performance clock fanout buffer. The input Two differential reference clock input pairs clock can be selected from two differential inputs or one crystal input. Differential input pairs can accept the following input The internal oscillator circuit is automatically disabled if the crystal levels: LVPECL, LVDS, HCSL, HSTL and Single-ended input is not selected. The crystal pin can be driven by a single-ended Crystal Oscillator Interface clock.The selected signal is distributed to six differential outputs which can be configured as LVPECL, LVDS or HCSL outputs. In Crystal input frequency range: 10MHz to 40MHz addition, an LVCMOS output is provided. All outputs can be disabled Maximum Output Frequency into an high-impedance state. The device is designed for a signal LVPECL - 2GHz fanout of high-frequency, low phase-noise clock and data signal. The LVDS - 2GHz outputs are at a defined level when inputs are open or tied to ground. HCSL - 250MHz It is designed to operate from a 3.3V or 2.5V core power supply, and LVCMOS - 250MHz either a 3.3V or 2.5V output operating supply. Two banks, each has three differential output pairs that can be configured as LVPECL or LVDS or HCSL One single-ended reference output with synchronous enable to avoid clock glitch Output skew: 80ps (maximum) (Bank A and Bank B at the same output level) Part-to-part skew: 200ps (typical) Additive RMS phase jitter 156.25MHz, (12kHz - 20MHz): 34.7fs (typical), 3.3V/ 3.3V Supply voltage modes: V /V DD DDO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging 2016 Integrated Device Technology, Inc. 1 May 20, 20168T39S06A Datasheet Block Diagram PullDown PullDown PullDown PullDown 2016 Integrated Device Technology, Inc. 2 May 20, 2016