Product Information

8V97051NLGI

8V97051NLGI electronic component of Renesas

Datasheet
Clock Synthesizer / Jitter Cleaner Wideband RF Syn Dual 34.375 to 4400MHz

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 12.121 ea
Line Total: USD 12.12

369 - Global Stock
Ships to you between
Wed. 15 May to Fri. 17 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
127 - WHS 1


Ships to you between Wed. 15 May to Fri. 17 May

MOQ : 1
Multiples : 1

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8V97051NLGI
Renesas

1 : USD 10.948
10 : USD 10.189
25 : USD 9.5565
100 : USD 8.6595
250 : USD 8.234
490 : USD 7.8315
980 : USD 7.475

     
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RoHS - XON
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Low Power Wideband Fractional 8V97051 RF Synthesizer / PLL Datasheet Description Features The 8V97051 is a high-performance Wideband RF Synthesizer / PLL Dual Differential Outputs optimized for use as the local oscillator (LO) in Multi-Carrier, Output frequency range: 34.375MHz to 4400MHz (continuous Multi-mode FDD, and TDD Base Station radio card. It is offered in a range) compact 5 5, 32-VFQFN package. RF Output Divide by 1, 2, 4, 8, 16, 32, 64 The 8V97051 Wideband RF Synthesizer / PLL offers a default Open Drain Outputs (see Output Distribution Section) Fractional Mode with the option to use it with an Integer mode. It requires an external loop filter. Fractional-N synthesizer (also supports Integer-N mode) 16-bit integer and 12-bit fractional The 8V97051 has an integrated Voltage Controlled Oscillator (VCO) (16-bit fractional when using the extended registers) that supports output frequencies from 34.375MHz to 4400MHz, and maintains superior phase noise and spurious performance. 3- or 4-wire SPI interface (compatible with 3.3V and 1.8V) Single 3.3V supply RF OUT output drivers have independently programmable A:B output power ranging from 4dBm to +7dBm. The RF OUT outputs Logic compatibility: 1.8V can be muted. The mute function is accessible via a SPI command Programmable output power level: -4dBm to +5dBm or mute pin. (up to +7 when using the extended registers) The operation of the 8V97051 is controlled by writing to registers Mute Function through a three-wire SPI interface. The device also has an additional Ultra low PN for 1.1GHz LO: -143dBc/Hz at 1MHz Offset, (typical) option that allows users to read back values from registers by configuring the MUX OUT pin as a SDO for the SPI interface. The Lock Detect Indicators SPI interface is compatible with 1.8V logic and tolerant to 3.3V. Input Reference frequency: 5MHz to 310MHz In multi-service base stations, very low noise oscillators are required Power Consumption: 380mW (typical) (RF OUT disabled) B to generate a large variety of frequencies to the mixers while 32-Lead, 5 5 VFQFN package maintaining excellent phase noise performance and low power. The 8V97051 offers a large tuning range capable of providing multi-band Automatic VCO band selection (Autocal feature) local oscillator (LO) frequency synthesis in multi-mode base stations, -40C to +85C ambient operating temperature thus limiting the use of multiple narrow band RF Synthesizers and reducing the BOM complexity and cost. The device can operate over Supports case temperature 105C operations -40C to +85C industrial temperature range. Lead-free (RoHS 6) packaging Applications Wireless Infrastructure Test Equipment CATV Equipment Military and Aerospace Wireless LAN Clock Generation 2018 Integrated Device Technology, Inc. 1 December 5, 20188V97051 Datasheet Table of Contents Description 1 Applications 1 Features 1 8V97051 Block Diagram 6 Pin Assignment .6 Pin Description and Characteristic Tables 7 Table 1. Pin Description .7 Table 2. Pin Characteristics 8 Table 3. Supply Pins and Associated Current Return Paths .8 Principles of Operation .9 Synthesizer Programming 9 Reference Input Stage .9 Reference Doubler 9 Table 4A. Lock Detect Precision (LDP) .9 Feedback Divider .9 Figure 1. RF Feedback N Divider .10 Table 4B. Fractional Spurs Due to the Quantization Noise .10 Phase and Frequency Detector (PFD) and Charge Pump 11 Figure 2. Simplified PFD Circuit using D-type Flip-flop 11 PFD Frequency 11 External Loop Filter .11 Phase Detector Polarity .11 Charge Pump High-Impedance .11 Integrated Low Noise VCO .11 Output Distribution Section .11 Figure 3. Output Clock Distribution 12 Figure 4. Output Stage .12 Output Matching .12 Figure 5. Broadband Matching Termination .12 Figure 6. Optimal Matching Termination 12 Band Selection Disable 12 Phase Adjust 13 Phase Resync .13 Figure 7. 12-bit Counter for Fast Lock and Phase Resync 13 Fast Lock Function .13 Figure 8. Example of Fast Lock Mode Loop Filter Topology 14 RF Output Power 14 MUX OUT 14 Table 4C. MUX OUT Pin Configuration 14 Power-Down Mode .14 Default Power-Up Conditions .14 Program Modes 14 Table 4D. Control Bits Configuration 14 2018 Integrated Device Technology, Inc. 2 December 5, 2018

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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