ICS9112A-16 TM Low Skew Output Buffer General Description Features The ICS9112A-16 is a high performance, low skew, low Zero input - output delay jitter clock driver. It uses a phase lock loop (PLL) Frequency range 25 - 133 MHz (3.3V) technology to align, in both phase and frequency, the REF High loop filter bandwidth ideal for Spread input with the CLKOUT signal. It is designed to distribute Spectrum applications. high speed clocks in PC systems operating at speeds Less than 200 ps Jitter between outputs from 25 to Skew controlled outputs 133 MHz. Skew less than 250 ps between outputs Available in 8 pin 150 mil SOIC ICS9112A-16 is a zero delay buffer that provides or 173 mil TSSOP package. synchronization between the input and output. The synchronization is established via CLKOUT feed back to 3.3V 10% operation the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS9112A-16 comes in an eight pin 150 mil SOIC or 173 mil TSSOP package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. Block Diagram Pin Configuration 8 pin SOIC, TSSOP 1337L12/09/08ICS9112A-16 Pin Descriptions PEIN NUMBERPEIN NAMTNYP DESCRIPTIO 2 1FREI.N Input reference frequency 3 22CLKOtUT Buffered clock outpu 3 31CLKOtUT Buffered clock outpu 4DGRN PdW Groun 3 53CLKOtUT Buffered clock outpu 6DVRDP)W Power Supply (3.3V 3 74CLKOtUT Buffered clock outpu 3 8TCLKOUOnUT Buffered clock output. Internal feedback on this pi Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 1337L12/09/08 2