ICS9112-17 Integrated Circuit Systems, Inc. Low Skew Output Buffer General Description Features The ICS9112-17 is a high performance, low skew, low jitter Zero input - output delay zero delay buffer. It uses a phase lock loop (PLL) Frequency range 25 - 133 MHz (3.3V) technology to align, in both phase and frequency, the REF High loop filter bandwidth ideal for Spread Spectrum input with the CLKOUT signal. It is designed to distribute applications. high speed clocks in PC systems operating at speeds Less than 200 ps cycle to cycle Jitter from 25 to 133 MHz. Skew controlled outputs Skew less than 250 ps between outputs ICS9112-17 is a zero delay buffer that provides Available in 16 pin, 150 mil SSOP & SOIC package synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS9112-17 has two banks of four outputs controlled Pin Configuration by two address lines. Depending on the selected address line, bank B or both banks can be put in a tri-state mode. In this mode, the PLL is still running and only the output buffers are put in a high impedance mode. The test mode shuts off the PLL and connects the input directly to the output buffers (see table below for functionality). The ICS9112-17 comes in a sixteen pin 150 mil SOIC or 16 pin SSOP package. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. 16 pin SSOP & SOIC Block Diagram Functionality CLKA CLKB Output PLL F1S2 FS CLKOUT (1, 4) (1, 4) Source Shutdown 00TeristateTnristatDLrive PNL 01DerivenTnristatDLrive PNL PLL PLL PLL 10 Bypass Bypass BypassRYEF Mode Mode Mode 11DnrivenDnriveDLrive PNL 0051K11/02/04ICS9112-17 Pin Descriptions PEIN NUMBERPEIN NAMTNYP DESCRIPTIO 2 1FRE I.N Input reference frequency 3 21CLKAOAUT Buffered clock output, Bank 3 32CLKAOAUT Buffered clock output, Bank 4D, 13VRD P)W Power Supply (3.3V 5D, 12GRN PdW Groun 3 61CLKBOBUT Buffered clock output. Bank 3 72CLKBOBUT Buffered clock output. Bank 4 82FS I2N Select input, bit 4 91FS I1N Select input, bit 3 130 CLKBOBUT Buffered clock output. Bank 3 141 CLKBOBUT Buffered clock output. Bank 3 134 CLKAOAUT Buffered clock output, Bank 3 145 CLKAOAUT Buffered clock output, Bank 3 1T6 CLKOUOnUT Buffered clock output, internal feedback on this pi Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 4. Weak pull-ups on these inputs 0051K11/02/04 2