7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer 9DBU0731 DATASHEET Description Features/Benefits The 9DBU0731 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 14 resistors compared to standard (ULP) PCIe family. The device has 7 output enables for clock HCSL outputs management, and 3 selectable SMBus addresses. 36mW typical power consumption eliminates thermal concerns Recommended Application Outputs can optionally be supplied from any voltage 1.5V PCIe Gen1-2-3 Fanout Buffer (FOB) between 1.05V and 1.5V maximum power savings Spread Spectrum (SS) compatible allows SS for EMI Output Features reduction 7 1167MHz Low-Power (LP) HCSL DIF pairs OE pins for each output support DIF power management HCSL-compatible differential input can be driven by Key Specifications common clock sources DIF additive cycle-to-cycle jitter < 5ps SMBus-selectable features optimize signal integrity to DIF output-to-output skew < 60ps application DIF additive phase jitter is < 300fs rms for PCIe Gen3 slew rate for each output DIF additive phase jitter < 350s rms for SGMII differential output amplitude Device contains default configuration SMBus interface not required for device operation 3.3V tolerant SMBus interface works with legacy controllers Three selectable SMBus addresses multiple devices can easily share an SMBus segment 5 5 mm 40-VFQFPN package minimal board space Block Diagram vOE(6:0) 7 DIF6 CLK IN DIF5 CLK IN DIF4 vSADR DIF3 DIF2 CKPWRGD PD CONTROL LOGIC SDATA 3.3 DIF1 SCLK 3.3 DIF0 9DBU0731 MARCH 8, 2017 1 2017 Integrated Device Technology, Inc.9DBU0731 DATASHEET Pin Configuration 40 39 38 37 36 35 34 33 32 31 vSADR tri130 NC vOE6 vOE3 229 DIF6328 DIF3 DIF6 427 DIF3 VDDR1.5529DBU07316 VDDIO CLK IN625 VDDO1.5 ePad is GND CLK IN vOE2 724 GNDDIG823 DIF2 SCLK 3.3922 DIF2 SDATA 3.3 10 21 vOE1 11 12 13 14 15 16 17 18 19 20 40-VFQFPN, 5mm x 5mm 0.4mm pin pitch prefix indicates internal Pull-Up Resistor v prefix indicates Internal Pull-Down Resistor SMBus Address Selection Table + Read/Write bit SADR Address x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 0X X X LowLow 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low Power Connections Pin Number Description VDD VDDIO GND Input 541 receiver analog 11 8 Digital Power 12,17,26,32, DIF 16,25,31 41 39 outputs,Logic 7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER 2 MARCH 8, 2017 VDDDIG1.5 CKPWRGD PD VDDIO VDDIO vOE0 vOE5 DIF0 DIF5 DIF0 DIF5 VDD1.5 vOE4 VDDIO DIF4 DIF1 DIF4 DIF1 VDDIO NC VDD1.5