REF1.8 DATASHEET 4-OUTPUT VERY LOW POWER PCIE GEN 14 CLOCK GENERATOR 9FGV0441 Description Features/Benefits The 9FGV0441 is an 4-output very low power clock Integrated terminations provide 100 differential Zo generator for PCIe Gen 1, 2, 3 and 4 applications with reduced component count and board space integrated output terminations providing Zo = 100 . The 1.8V operation reduced power consumption device has 4 output enables for clock management and OE pins support DIF power management supports 2 different spread spectrum levels in addition to LP-HCSL differential clock outputs reduced power and spread off. board space Programmable slew rate for each output allows tuning Recommended Application for various line lengths PCIe Gen14 clock generation for Riser Cards, Storage, Programmable output amplitude allows tuning for Networking, JBOD, Communications, Access Points various application environments Output Features DIF outputs blocked until PLL is locked clean system start-up 4 0.7V low-power HCSL-compatible (LP-HCSL) DIF Selectable 0%, -0.25% or -0.5% spread on DIF outputs pairs with Zo=100 reduces EMI 1 1.8V LVCMOS REF output with Wake-On-Lan (WOL) External 25MHz crystal supports tight ppm with 0 ppm support synthesis error Key Specifications Configuration can be accomplished with strapping pins SMBus interface not required for device control DIF cycle-to-cycle jitter < 50ps 3.3V tolerant SMBus interface works with legacy DIF output-to-output skew < 50ps controllers DIF phase jitter is PCIe Gen14 compliant Space saving 5 x 5 mm 32-VFQFPN minimal board REF phase jitter is < 1.5ps RMS space Selectable SMBus addresses multiple devices can easily share an SMBus segment Block Diagram X1 25 OSC X2 OE(3:0) 4 SS Capable PLL DIF(3:0) SADR SS EN tri CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 IDT 4-OUTPUT VERY LOW POWER PCIE GEN 14 CLOCK GENERATOR 1 9FGV0441 JUNE 6, 20199FGV0441 4-OUTPUT VERY LOW POWER PCIE GEN 14 CLOCK GENERATOR Pin Configuration 32 31 30 29 28 27 26 25 GNDXTAL 1 24 vOE2 XIN/CLKIN 25 2 DIF2 23 X2 3 DIF2 22 VDDXTAL1.8 4 VDDA1.8 21 9FGV0441 VDDREF1.8 5 GNDA 20 vSADR/REF1.8 6 DIF1 19 GNDREF 7 18 DIF1 GNDDIG 817vOE1 9 10111213141516 32-VFQFPN, 5 x 5 mm, 0.5mm pitch prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull down-resistor SMBus Address Selection Table + Read/Write Bit SADR Address x State of SADR on first application 0 1101000 of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx REF CKPWRGD PD OE bit OEx True O/P Comp. O/P 1 0 X X Low Low Hi-Z 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD GND 41 XTAL Analog 57 REF Output 98, 30 Digital Power 16, 25 15, 26 DIF outputs 21 20 PLL Analog IDT 4-OUTPUT VERY LOW POWER PCIE GEN 14 CLOCK GENERATOR 2 9FGV0441 JUNE 6, 2019 VDDDIG1.8 vSS EN tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 DIF0 DIF3 DIF0 DIF3 GND GND VDDO1.8 VDDO1.8