2.5 V/3.3 VECL 2, 4, 8 Clock Generation Chip MC100LVEP34 Description The MC100LVEP34 is a low skew 2, 4, 8 clock generation chip www.onsemi.com designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The V pin, an internally BB MARKING generated voltage supply, is available to this device only. For DIAGRAMS* single ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also BB BB rebias AC coupled inputs. When used, decouple V and V via BB CC 16 a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. 16 100LVEP34G When not used, V should be left open. BB 1 AWLYWW The common enable (EN) is synchronous so that the internal SO16 dividers will only be enabled/disabled when the internal clock is D SUFFIX 1 already in the LOW state. This avoids any chance of generating a runt CASE 751B clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse 16 could lead to losing synchronization between the internal divider 100 16 stages. The internal enable flipflop is clocked on the falling edge of VP34 the input clock therefore, all associated specification limits are ALYW 1 referenced to the negative edge of the clock input. TSSOP16 1 Upon startup, the internal flipflops will attain a random state the DT SUFFIX master reset (MR) input allows for the synchronization of the internal CASE 948F dividers, as well as multiple LVEP34s in a system. Singleended CLK input operation is limited to a V 3.0 V in PECL mode, CC A = Assembly Location or V 3.0 V in NECL mode. L, WL = Wafer Lot EE Y = Year Features W, WW = Work Week G or = PbFree Package 35 ps OutputtoOutput Skew (Note: Microdot may be in either location) Synchronous Enable/Disable *For additional marking information, refer to Master Reset for Synchronization Application Note AND8002/D. The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: V = 2.375 V to 3.8 V CC with V = 0 V EE ORDERING INFORMATION NECL Mode Operating Range: V = 0 V CC with V = 2.375 V to 3.8 V Device Package Shipping EE Open Input Default State SOIC16 48 Units / MC100LVEP34DG (PbFree) Tube LVDS Input Compatible MC100LVEP34DTG 96 Units / TSSOP16 These Devices are PbFree, Halogen Free/BFR Free and are RoHS Tube (PbFree) Compliant 2500 / MC100LVEP34DTR2G TSSOP16 Tape & Reel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: April, 2021 Rev. 12 MC100LVEP34/DMC100LVEP34 V Q0 1 16 CC Q 2 Q0 EN 15 2 R Q D V NC CC 3 14 R Q1 CLK 4 13 Q 4 CLK Q1 12 5 R V V CC BB 6 11 MR Q2 7 10 Q 8 V Q2 EE 8 9 R Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. 16 Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Table 2. FUNCTION TABLE Pin Function CLK EN MR FUNCTION CLK*, CLK** ECL Diff Clock Inputs Z L L Divide ZZ H L Hold Q 0 3 EN* ECL Sync Enable X X H Reset Q 0 3 MR* ECL Master Reset Z = LowtoHigh Transition ZZ = HightoLow Transition Q0, Q0 ECL Diff 2 Outputs Q1, Q1 ECL Diff 4 Outputs Q2, Q2 ECL Diff 8 Outputs V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE NC No Connect * Pins will default LOW when left open. **Pins will default to V /2 when left open. CC www.onsemi.com 2