9P936AFLF Renesas

DATASHEET ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Description Pin Configuration Dual DDR I/II fanout buffer for VIA Chipset AVDD2.5 GND 128 VDDQ2.5/1.8 AGND 227 Output Features BUF INT326 AVDD2.5 Low skew, fanout buffer BUF INC AGND 425 SMBus for functional and output control DDRT0 DDRT5 524 Single bank 1-6 differential clock distribution DDRC5 DDRC0 623 1 pair of differential feedback pins for input to output synchronization DDRT1 722 GND Supports up to 2 DDR DIMMs DDRC1 VDDQ2.5/1.8 821 266MHz (DDRI 533) output frequency support DDRT4 GND 920 400MHz (DDRII 800) output frequency support VDDQ2.5/1.8 DDRC4 10 19 Programmable skew through SMBus DDRT3 FB OUTT 11 18 Individual output control programmable through SMBus FB OUTC DDRC3 12 17 DDRT2 SDATA 13 16 DDRC2 SCLK 14 15 Key Specifications 28-SSOP & TSSOP OUTPUT - OUTPUT skew: <100ps Output Rise and Fall Time for DDR outputs: 650ps - 950ps DUTY CYCLE: 47% - 53% 28-pin SSOP/TSSOP package RoHS compliant packaging Funtional Block Diagram BUF INC BUF INT Control SCLK FB OUTC SDATA Logic FB OUTT DDRC (5:0) DDRT (5:0) TM TM IDT /ICS Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 ICS9P936ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer Pin Description PIN PIN NAME PIN TYPE DESCRIPTION 1 AVDD2.5 PWR 2.5V Analog Power pin for Core PLL 2 AGND PWR Analog Ground pin for Core PLL 3 BUF INT IN True Buffer In signal for memory outputs. 4 BUF INC IN Complementary Buffer In signal for memory outputs. 5 DDRT0 OUT -40 6 DDRC0 OUTComplementar Clock of differential pair output. 7 DDRT1 OUTTru Clock of differential pair output. 8 DDRC1 OUTComplementar Clock of differential pair output. 9 GND PWR Ground pin. 10 VDDQ2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively True single-ended feedback output, dedicated external feedback. It switches 11 FB OUTT OUT at the same frequency as other DDR outputs. Complementary single-ended feedback output, dedicated external feedback. 12 FB OUTC OUT It switches at the same frequency as other DDR outputs. 13 DDRT2 OUTTru Clock of differential pair output. 14 DDRC2 OUTComplementar Clock of differential pair output. 15 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 16 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant. 17 DDRC3 OUTComplementar Clock of differential pair output. 18 DDRT3 OUTTru Clock of differential pair output. 19 DDRC4 OUTComplementar Clock of differential pair output. 20 DDRT4 OUTTru Clock of differential pair output. 21 VDDQ2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively 22 GND PWR Ground pin. 23 DDRC5 OUTComplementar Clock of differential pair output. 24 DDRT5 OUTTru Clock of differential pair output. 25 AGND PWR Analog Ground pin for Core PLL 26 AVDD2.5 PWR 2.5V Analog Power pin for Core PLL 27 VDDQ2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively 28 GND PWR Ground pin. TM TM IDT /ICS Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09 2