19-Output DB1900Z for PCIe Gen1-4 and 9ZX21901D QPI/UPI DATASHEET Description Features The 9ZX21901D is a second generation DB1900Z differential Fixed feedback path 0ps input-to-output delay buffer for Intel Purley and newer platforms. The part is 9 Selectable SMBus addresses multiple devices can share backwards compatible to the 9ZX21901C while offering much same SMBus segment improved phase jitter performance. A fixed external feedback 8 dedicated OE pins hardware control of outputs maintains low drift for critical QPI/UPI applications. In bypass PLL or bypass mode PLL can dejitter incoming clock mode, the 9ZX21901D can provide outputs up to 400MHz. Selectable PLL BW minimizes jitter peaking in downstream PLL s PCIe Clocking Architectures Supported Hardware or software control of PLL operating mode Common Clocked (CC) change mode with software mode does not need power Separate Reference No Spread (SRNS) cycle Separate Reference Independent Spread (SRIS) Spread spectrum compatible tracks spreading input clock for EMI reduction Typical Applications SMBus Interface unused outputs can be disabled Servers, Storage, Networking 100MHz and 133.33MHz PLL mode legacy QPI support Output Features 72-QFN 10 x 10 mm package small board footprint 19 HCSL output pairs Key Specifications Cycle-to-cycle jitter: < 50ps Output-to-output skew: < 50ps Input-to-output delay: Fixed at 0 ps Input-to-output delay variation: < 50ps Phase jitter: PCIe Gen4 < 0.5ps rms Phase jitter: UPI 9.6GB/s < 0.1ps rms Functional Block Diagram Low Phase DFB OUT Noise Z-PLL (SS- DIF IN Compatible) DIF 18 OE(12:5) Bypass path HIBW BYPM LOBW 19 outputs 100M 133M CKPWRGD/PD SMB A0 tri SMB A1 tri SMBDAT SMBCLK DIF 0 IREF 9ZX21901D APRIL 17, 2018 1 2018 Integrated Device Technology, Inc. CONTROLDIF 6 DIF 6 OE5 DIF 5 DIF 5 VDD DIF 4 DIF 4 DIF 3 DIF 3 GND DIF 2 DIF 2 DIF 1 DIF 1 VDD DIF 0 DIF 0 9ZX21901D DATASHEET Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDDA 1 54 OE11 GNDA 2 53 DIF 11 IREF 3 52 DIF 11 100M 133M 4 51 OE10 HIBW BYPM LOBW 5 50 DIF 10 CKPWRGD PD 6 49 DIF 10 GND 7 48 OE9 9ZX21901D VDDR 8 47 DIF 9 connect ePad to Ground DIF IN 9 46 DIF 9 NOTE: DFB OUT pins must be DIF IN 10 45 VDD terminated identically to the regular DIF SMB A0 tri 11 44 GND outputs SMBDAT 12 43 OE8 SMBCLK 13 42 DIF 8 SMB A1 tri 14 41 DIF 8 NC 15 40 OE7 NC 16 39 DIF 7 DFB OUT 17 38 DIF 7 DFB OUT 18 37 OE6 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72-pin VFQFPN (10mm x10 mm, 0.5mm pad pitch) Functionality at Power Up (PLL Mode) Power Connections DIF IN DIF x Pin Number 100M 133M Description (MHz) (MHz) VDD GND 1 100.00 DIF IN 12 Analog PLL 0 133.33 DIF IN 8 7 Analog Input 21, 31, 45, 26, 44, 63 DIF clocks 58, 68 PLL Operating Mode Readback Table HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 Low (Low BW) 0 0 9ZX21901 SMBus Addressing Mid (Bypass) 0 1 Pin SMBus Address High (High BW) 1 1 SMB A1 tri SMB A0 tri (Rd/Wrt bit = 0) 0 D8 0 0M DA PLL Operating Mode 1 0 DE HiBW BypM LoBW MODE M0 C2 Low PLL Lo BW M M C4 Mid Bypass 1 M C6 High PLL Hi BW 0 1 CA NOTE: PLL is OFF in Bypass Mode M 1 CC 11 CE Tri-level Input Thresholds Level Voltage Low <0.8V Mid 1.2<Vin<1.8V High Vin > 2.2V 19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI 2 APRIL 17, 2018 DIF 18 DIF 18 DIF 17 DIF 17 VDD DIF 16 DIF 16 DIF 15 DIF 15 GND DIF 14 DIF 14 DIF 13 DIF 13 VDD OE12 DIF 12 DIF 12