6-Output DB800ZL Derivative with 9ZXL0651 Integrated 85ohm Terminations Datasheet Description Features The 9ZXL0651 is a low-power 6-output differential buffer 25MHz PFT clock delay management that meets all the performance requirements of the Intel Low-Power-HCSL outputs with Zo = 85 save power DB1200Z specification. It consumes 50% less power than and board space no termination resistors required. standard HCSL devices and has internal terminations to Ideal for blade servers. allow direct connection to 85 transmission lines. It is Space-saving 40-pin VFQFPN package suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for Fixed feedback path for 0ps input-to-output delay demanding QPI/UPI applications. 6 OE pins hardware control of each output PLL or bypass mode PLL can dejitter incoming clock Applications Selectable PLL bandwidth minimizes jitter peaking in Buffer for Romley, Grantley and Purley Servers, SSDs and downstream PLLs PCIe Spread spectrum compatible tracks spreading input clock for low EMI Output Features 6 LP-HCSL Output Pairs w/integrated terminations Key Specifications (Zo = 85 ) Cycle-to-cycle jitter < 50ps Output-to-output skew < 65ps Input-to-output delay variation < 50ps PCIe Gen3 phase jitter < 1.0ps RMS QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS Block Diagram OE(5:0) DFB OUT NC Z-PLL (SS Compatible) DIF IN DIF(5:0) DIF IN HIBW BYPM LOBW CKPWRGD/PD Logic SMBDAT SMBCLK 2021 Renesas Electronics Corporation 1 January 28, 20219ZXL0651 Datasheet Pin Configuration 40 39 38 37 36 35 34 33 32 31 VDDA139ZXL06510 NC vHIBW BYPM LOBW 229 VDD CKPWRGD PD 328 vOE3 GND427 DIF 3 VDDR526 DIF 3 EPAD is GND DIF IN625 VDD DIF IN 724 DIF 2 SMBDAT823 DIF 2 SMBCLK922 vOE2 DFB OUT NC 10 21 VDD 11 12 13 14 15 16 17 18 19 20 40-VFQFPN prefix indicates internal Pull-Up Resistor v prefix indicates Internal Pull-Dow n Resistor v prefix indicates Internal Pull-Up/Dow n Resistor (biased to VDD/2) 5mm x 5mm 0.4mm pin pitch Power Management Table PLL STATE IF NOT IN DIF IN/ SMBus DIF(5:0)/ BYPASS CKPWRGD PD DIF IN EN bit DIF(5:0) MODE 0X XLow/LowOFF 0Low/Low ON 1 Running 1 Running ON PLL Operating Mode PLL Operating Mode Readback Table HiBW BypM LoBW MODE HiBW BypM LoBW Byte0, bit 7 Byte 0, bit 6 Low PLL Lo BW Low (Low BW) 0 0 Mid Bypass Mid (Bypass) 0 1 High PLL Hi BW High (High BW) 1 1 NOTE: PLL is OFF in Bypass Mode Tri-level Input Thresholds Power Connections Level Voltage Pin Number <0.8V Low VDD GND Description Mid 1.2<Vin<1.8V 141 Analog PLL High Vin > 2.2V 5 4 Analog Input 12,16,20,24,27 9ZXL0651 SMBus Address 41 DIF clocks ,31,32,36,40 1101100 + Read/Write bit 2021 Renesas Electronics Corporation 2 January 28, 2021 DFB OUT NC NC VDD VDD vOE0 vOE5 DIF 0 DIF 5 DIF 0 DIF 5 VDD VDD DIF 1 DIF 4 DIF 1 DIF 4 vOE1 vOE4 VDD VDD