DATASHEET 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1530 Description Features/Benefits The 9ZXL1530 is a 15-output version of the Intel DB1900Z Fixed feedback path 0ps input-to-output delay Differential Buffer utilizing Low-Power HCSL (LP-HCSL) 9 Selectable SMBus addresses Multiple devices can outputs to reduce power consumption more than 50% from share same SMBus segment the original IDT9ZX21501. It is suitable for PCI-Express Separate VDDIO for outputs allows maximum power Gen1/2/3 or QPI/UPI applications, and uses a fixed external savings feedback to maintain low drift for demanding QPI/UPI applications. PLL or bypass mode PLL can dejitter incoming clock Selectable PLL BW minimizes jitter peaking in downstream PLL s Recommended Application Spread spectrum compatible tracks spreading input Buffer for Romley, Grantley and Purley Servers clock for EMI reduction SMBus Interface unused outputs can be disabled Key Specifications 100MHz & 133.33MHz PLL mode Legacy QPI/UPI Cycle-to-cycle jitter: < 50ps support Output-to-output skew: <65ps Differential outputs are Low/Low in power down Input-to-output delay: Fixed at 0 ps Maximum power savings Input-to-output delay variation: <50ps Phase jitter: PCIe Gen3 < 1ps rms Output Features Phase jitter: QPI 9.6GB/s < 0.2ps rms 15 - LP-HCSL Differential Output Pairs Block Diagram FBOUT NC Z-PLL DIF(14:0) (SS Compatible) DIF IN DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK IDT 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 1 9ZXL1530 REV D 112015GND VDDIO DIF 4 DIF 4 DIF 3 DIF 3 VDD GND DIF 2 DIF 2 DIF 1 DIF 1 GND VDDIO DIF 0 DIF 0 9ZXL1530 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA 48 VDDIO 1 GNDA247 GND 100M 133M 346 DIF 9 HIBW BYPM LOBW 4 45 DIF 9 CKPWRGD PD 544 DIF 8 GND643 DIF 8 VDDR742 GND DIF IN841 VDD 9ZXL1530 DIF IN 940 DIF 7 SMB A0 tri DIF 7 10 39 11 38 SMBDAT DIF 6 SMBCLK 12 37 DIF 6 13 36 SMB A1 tri VDDIO FBOUT NC 14 35 GND FBOUT NC 15 34 DIF 5 GND 16 33 DIF 5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note: Pins with prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm Power Management Table Inputs Control Bits Outputs DIF IN/ SMBus DIF x/ FBOUT NC/ PLL State CKPWRGD PD DIF IN EN bit DIF x FBOUT NC 0 X X Low/Low Low/Low OFF 0 Low/Low Running ON 1 Running 1 Running Running ON Power Connections PLL Operating Mode Pin Number HiBW BypM LoBW Byte0, bit (7:6) Description VDD VDDIO GND Low ( PLL Low BW) 00 1 2 Analog PLL Mid (Bypass) 01 7 6 Analog Input High (PLL High BW) 11 16,20,25,32,3 NOTE: PLL is off in Bypass mode 19,31,36,48,51 26, 41, 58 DIF clocks 5,42,47,52,57 ,63 ,64 Tri-Level Input Thresholds Level Voltage Functionality at Power-up (PLL mode) Low <0.8V Mid 1.2<Vin<1.8V DIF IN DIFx 100M 133M High Vin > 2.2V (MHz) (MHz) 1 100.00 DIF IN 0 133.33 DIF IN IDT 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 2 9ZXL1530 REV D 112015 GND VDDIO DIF 14 DIF 14 DIF 13 DIF 13 VDD GND DIF 12 DIF 12 DIF 11 DIF 11 GND VDDIO DIF 10 DIF 10