DATASHEET 80C86 FN2957 Rev 5.00 CMOS 16-Bit Microprocessor Jul 13, 2018 The 80C86 high performance 16-bit CMOS CPU is Features manufactured using a self-aligned silicon gate CMOS Compatible with NMOS 8086 process (Scaled SAJI IV). Two modes of operation, minimum for small systems and maximum for larger Completely static CMOS design applications such as multiprocessing, allow user - DC 8MHz (80C86-2) configurations to achieve the highest performance level. Full Low power operation TTL compatibility (with the exception of CLOCK) and - lCCSB 500mA max industry standard operation allow use of existing NMOS - ICCOP 10mA/MHz typ 8086 hardware and software designs. 1MByte of direct memory addressing capability Related Literature 24 operand addressing modes For a full list of related documents, visit our website Bit, Byte, Word and Block Move operations 80C8 6 product page 8-Bit and 16-Bit signed/unsigned arithmetic - Binary, or decimal - Multiply and divide Wide operating temperature range - C80C86 0C to +70C - M80C86 . -55C to +125C Pb-free available (RoHS compliant) Ordering Information PART NUMBER PART MARKING TEMP. RANGE (C) PACKAGE PKG. DWG. CP80C86-2Z (Note 1) CP80C86-2Z 0 to +70 40 Ld PDIP (Note 2) E40.6 (RoHS compliant) MD80C86-2/883 MD80C86-2/883 -55 to +125 40 Ld CERDIP F40.6 MD80C86-2/B MD80C86-2/B -55 to +125 40 Ld CERDIP F40.6 8405202QA 8405202QA -55 to +125 40 Ld CERDIP (SMD) F40.6 NOTES: 1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN2957 Rev 5.00 Page 1 of 39 Jul 13, 201880C86 Table of Contents Functional Diagram . 3 Pin Descriptions 4 Minimum Mode System 6 Maximum Mode System 6 Functional Description 8 Static Operation 8 Internal Architecture .8 Memory Organization 8 Minimum and Maximum Operation Modes . 9 Bus Operation . 9 I/O Addressing 10 External Interface 12 Processor RESET and Initialization 12 Bus Hold Circuitry . 13 Interrupt Operations 13 Non-Maskable Interrupt (NMI) 13 Maskable Interrupt (INTR) . 13 Halt 14 Read/Modify/Write (Semaphore) 14 Operations Using Lock 14 External Synchronization Using TEST 14 Basic System Timing . 14 System Timing - Minimum System 14 Bus Timing - Medium Size Systems . 15 Absolute Maximum Ratings . 17 Thermal Information 17 Operating Conditions . 17 DC Electrical Specifications . 17 Capacitance 18 AC Electrical Specifications Minimum Complexity SystemAC Electrical Specifications 18 Waveforms . 20 AC Electrical Specifications Maximum Mode SystemAC Electrical Specifications . 22 Waveforms . 25 AC Test Circuit 28 AC Testing Input, Output Waveform 28 Burn-In Circuits .29 Metallization Topology 30 Metallization Mask Layout . 30 Instruction Set Summary 31 Revision History . 36 Dual-In-Line Plastic Packages (PDIP) 37 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) 38 FN2957 Rev 5.00 Page 2 of 39 Jul 13, 2018