IP80C88-2

DATASHEET 80C88 FN2949 Rev.5.00 CMOS 8-/16-Bit Microprocessor Sep 28, 2017 The Intersil 80C88 high performance 8-/16-bit CMOS CPU is Features manufactured using a self-aligned silicon gate CMOS process Compatible with NMOS 8088 (Scaled SAJI IV). Two modes of operation, Minimum for small systems and Maximum for larger applications such as Direct software compatibility with 80C86, 8086, 8088 multiprocessing, allow user configuration to achieve the 8-bit data bus interface 16-bit internal architecture highest performance level. Completely static CMOS design Full TTL compatibility (with the exception of CLOCK) and - DC 5MHz (80C88) industry-standard operation allow use of existing NMOS 8088 - DC 8MHz (80C88-2) hardware and Intersil CMOS peripherals. Low power operation Complete software compatibility with the 80C86, 8086, and - ICCSB . 500A maximum 8088 microprocessors allows use of existing software in new designs. - ICCOP . 10mA/MHz maximum 1 MB of direct memory addressing capability Related Literature 24 operand addressing modes For a full list of related documents, visit our website Bit, byte, word, and block move operations - 80C88 product page 8-bit and 16-bit signed/unsigned arithmetic Bus-hold circuitry eliminates pull-up resistors Wide operating temperature ranges - C80C88 .0C to +70C - M80C88 .-55C to +125C Pb-free available (RoHS compliant) Ordering Information TEMPERATURE PART NUMBER PART PART NUMBER PART RANGE (5MHz) MARKING (8MHz) MARKING (C) PACKAGE PKG. DWG. MD80C88/B MD80C88/B -55 to +125 40 LD CERDIP F40.6 CP80C88Z CP80C88Z CP80C88-2Z 0 to +70 40 LD PDIP* E40.6 (Note) (Pb-Free) NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN2949 Rev.5.00 Page 1 of 39 Sep 28, 201780C88 Table of Contents Ordering Information 1 Pin Configurations . 3 Functional Diagram 4 Pin Descriptions (Minimum or Maximum Mode) 5 Pin Descriptions (Minimum Mode) . 6 Pin Description (Maximum Mode) 7 Functional Description . 8 Static Operation .8 Internal Architecture .8 Memory Organization 8 Minimum and Maximum Modes .9 Bus Operation . 10 I/O Addressing 12 External Interface 13 Processor Reset and Initialization 13 Bus Hold Circuitry 13 Interrupt Operations . 13 Non-Maskable Interrupt (NMI) . 13 Maskable Interrupt (INTR) 13 Halt . 14 Read/Modify/Write (Semaphore) Operations Via LOCK . 14 External Synchronization Via TEST . 14 Basic System Timing . 14 System Timing - Minimum System . 14 Bus Timing - Medium Complexity Systems 15 The 80C88 Compared to the 80C86 15 Absolute Maximum Ratings 17 Thermal Information 17 Operating Conditions . 17 Die Characteristics . 17 Electrical Specifications 17 Capacitance . 17 AC Electrical Specifications 18 Waveforms 20 AC Electrical Specifications 22 Waveforms 24 AC Test Circuit . 27 AC Testing Input, Output Waveform . 27 Burn-In Circuits . 27 Die Characteristics . 28 Metallization Mask Layout . 29 Instruction Set Summary 30 Revision History 37 About Intersil 37 Dual-In-Line Plastic Packages (PDIP) 38 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) . 39 FN2949 Rev.5.00 Page 2 of 39 Sep 28, 2017