USERS MANUAL ISL55110 11EVAL1Z, ISL55110 11EVAL2Z AN1283 Rev 0.00 Evaluation Board Users Manual February 13, 2007 Before Getting Started SCOPE PROBE CONNECTIONS This document supplements the ISL55110, ISL55111 Specification FN6228. Evaluation board users should review DIF+ that document to obtain information on the parts basic DIF- functionality and power requirements. A most important note is before powering up the board, review the Power Up DRIVER INPUT IN B - BNC TP-IN B Sequence in that specification. There are two DC sources R1 DIF+ utilized, so a user may inadvertently mis-apply the power 50 sources causing damage to the part. DIF- Take time to review the ISL55110, ISL55111 Data Sheet GND (FN6228) and become familiar with the parts basic functions and power options. Note also that FN6228 supersedes this R3 R5 OB - BNC 0 0 document with respect to updates and modifications. Always DIF+ C6 C8 refer to that document if discrepancies occur. NOT NOT DIF- POPULATED POPULATED TP-OB All ISL55110, ISL55111 QFN and TSSOP boards are GND DRIVER OUT designed essentially in the same fashion. This document FIGURE 1. DUAL.1 SPACED PINS ARE PLACED ON THE provides the user with the information regarding the EVALUATIONS BOARDS FOR LEADLESS ACTIVE PROBE CONNECTIONS evaluation board design, circuitry layout and driver load options. BNC Connections Scope Probe Connections This series of evaluation boards also provides BNC Another topic to cover before getting started is the evaluation connections for Input and Output signals. A key point to board physical connections for waveform observations. On remember is the ISL55110, ISL55111 Driver Outputs each schematic version you will see a component with pins (OA/OB) operate with the VH voltage as a High and Ground designated as DIF+ and DIF-. This is not an active as a Low. These connectors are laid out to accommodate component but a dual pin header physically designed to SMD connectors as well as BNCs. Also note that the Driver accommodate leadless connection of active differential or Inputs have 50 terminations that you may need to remove FET Probes. This will minimize ground lead inductance and for your application. capacitive loading while making waveform observations. However, the user must also be mindful of max voltage Power Down Feature limitations when using these types of probes. The ISL55110, All boards provide the same capability for testing the Power ISL55111 drivers cover a large voltage range, so double Down Feature. A SPDT- Center OFF switch is provided for check the probes specifications. manual testing of the feature. In one position the PD input is Scope Probe Test Points (TP) are provisioned across all connected to VDD (Power Down Enabled). In the other inputs, outputs and VDD/VH to ground. position the PD Input is connected to Ground. AN1283 Rev 0.00 Page 1 of 5 February 13, 2007Application Note 1283 ISL55110 11EVAL1Z, ISL55110 11EVAL2Z Once static observations check out, you can then increase S1 - POWER DOWN CONTROL SPDT - CENTER OFF VDD power current limits for VCC/VH and apply higher frequency PD - BNC inputs to the IN A/IN B pins. R7 GND 10k Layout Information GND All evaluation boards have complete silk-screen information regarding Test points, Jumpers and Component placements. VDD 1 VDD OB 8 2 PD GND 7 Schematic Information 3 IN-B VH 6 4 IN-A OA 5 Schematics are drawn with physical location in mind. Any changes in electrical circuitry will be updated in this ISL55110, ISL55111 TSSOP document as needed. FIGURE 2. TSSOP AND QFN EVALUATION BOARDS HAVE THE SAME POWER DOWN CIRCUITRY Included below are two schematics. ISL55110, ISL55111: Finally the center off position provides a means of TSSOP dual driver device and ISL55110, ISL55111 QFN connecting a repetitive signal source to the PD input. This is dual driver. Both packages have the Power Down Control, so that the user can observe Power Down Enable/Disable while the QFN has both Power Down and Enable inputs. timing. An important note to remember when using the PD - BNC: 1) Place the switch in Center-Off position. 2) The PD Driver Loads input is referenced to VDD and ground. DRIVER OUT OB OB - BNC R3 R5 S2 - POWER DOWN CONTROL 0 0 SPDT - CENTER OFF VDD EN - BNC DIF+ PD - BNC C6 C8 R7 GND NOT NOT DIF- 10k POPULATED POPULATED TP-OB S1- ENABLE CONTROL GND GND GND SPDT- CENTER OFF DRIVER OUT OA OA - BNC R4 R6 GND R8 0 0 10k DIF+ C7 C9 NOT NOT DIF- POPULATED POPULATED 12 VDD 1 VDD OB 11 GND /ENABLE TP-OA 2 10 GND VH 3 PD OA 9 4 IN-B FIGURE 4. CUSTOM LOAD COMPONENTS ISL55110, ISL55111 QFN Component locations C6 to C7 and R3 to R6 are surface mount locations provided so the user can experiment with FIGURE 3. QFN PACKAGES HAVE BOTH POWER DOWN various load configurations. AND OUTPUT ENABLE DIGITAL INPUTS Initial Power Up Please refer to the device specification for power up sequencing and current requirements. Also note that the frequency of operation of each driver will determine the current needed. There are graphs in the specification regarding current characteristics. When first powering up the device, set all power bus inputs to minimum current levels needed for quiescent operation. Check the device out statically with DC inputs on the IN A/ IN B pins and observe that the OA/OB outputs toggle when the Input pins rise above and below the logic thresholds. Please note that these inputs are intended for use by high speed logic. Avoid slow DC ramps. VDD current should be ~3.6mA and VH should be less then 100Amps with no DC loads on the outputs. AN1283 Rev 0.00 Page 2 of 5 February 13, 2007 5 IN-A