DATASHEET ISL6271A FN9171 Rev 2.00 Integrated XScale Regulator August 10, 2015 The ISL6271A is a versatile power management IC (PMIC) Features designed for the Xscale type of processors. The device 2 Three Voltage Regulators (1 Buck, 2 LDOs) integrates three regulators, two fault indicators and an I C High-Efficiency, fully-Integrated synchronous buck bus for communication with a host microprocessor. Two of regulator with DVM the three regulators function as low power, low drop out regulators, designed to power SRAM and phase-lock loop 800mA DC output current for the buck regulator circuitry internal to the Xscale processor. The third regulator Proprietary Synthetic Ripple Control Topology uses a proprietary switch-mode topology to power the Greater than 1MHz Switching Frequency processor core and facilitate Dynamic Voltage Management Diode emulation for light load efficiency (DVM), as defined by Intel. 2 I C Interface Module for DVM from 0.85V to 1.6V Since power dissipation inside a microprocessor is Optional fixed 4-bit VID-control in lieu of DVM proportional to the square of the core voltage, Intel XScale processors implement DVM as a means to more efficiently Small Output Inductor and Capacitor utilize battery capacity. To support this power saving Battery Fault signal 2 architecture, the ISL6271A integrates an I C bus for Input Supply Voltage Range: 2.76V-5.5V communication with the host processor. The processor, acting 4x4 mm QFN Package: as the bus master, transmits a voltage level and voltage - Compliant to JEDEC PUB95 MO-220 slew rate to the ISL6271A appropriate to the processing QFN - Quad Flat No Leads - Package Outline requirements higher core voltages support higher operating - Near Chip Scale Package footprint, which improves frequencies and code execution. The bus is fully compliant 2 PCB efficiency and has a thinner profile with the Phillips I C protocol and supports both standard and fast data transmission modes. Alternatively, the output of Pb-free Available (RoHS Compliant) the core regulator can be programmed in 50mV increments from 0.85V to 1.6V using the input Voltage ID (VID) pins. All Applications three regulators share a common enable pin and are PDA protected against overcurrent, over temperature and Cell Phone undervoltage conditions. When disabled via the enable pin, the ISL6271A enters a low power state that can be used to Tablet Devices conserve battery life while maintaining the last programmed Embedded Processors VID code and slew rate. An integrated soft-start circuit transitions the ISL6271A output voltages to their default Related Literature values at a rate determined by an external soft-start capacitor. Technical Brief TB379 Thermal Characterization of Packaged Semiconductor Devices Pinout Technical Brief TB389 PCB Land Pattern Design and ISL6271A (4x4 QFN) TOP VIEW Surface Mount Guidelines for QFN Packages Application Note AN1139 Setup Instruction for the ISL6271 Evaluation Kit 20 19 18 17 16 Ordering Information VCC LVCC 1 15 TEMP. PKG. VIDEN 2 14 VPLL PART NUMBER* RANGE (C) PACKAGE DWG. SCL/VID0 3 13 VSRAM ISL6271ACRZ (Note) -25 to 85 20 Ld 4x4 QFN L20.4x4 (Pb-free) SDA/VID1 4 12 FB *Add -T suffix for tape and reel. VID2 5 11 VOUT NOTE: Intersil Pb-free products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate 67 8 9 10 termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. FN9171 Rev 2.00 Page 1 of 17 August 10, 2015 VID3 SOFT PGND EN PHASE BFLT PVCC BBAT PGOOD GNDISL6271A Regulator Block Diagram LVCC LDO1 VSRAM (VCC SRAM) EN LDO2 VPLL (VCC PLL) PVCC SCL (VID 0) 2 I C SDA (VID 1) & SWITCHING STATIC DAC VID2 REGULATOR VID VOUT VID3 (VCC VCORE) LOGIC VIDEN FIGURE 1. BULVERDE POWER CONTROLLER Functional Block Diagram PGOOD BFLT BBAT VIDEN VCC 1.1V VSRAM 1.3V VPLL 1.8V TO 5.5V LVCC LDO1 AND LDO2 SCL/VID0 POR PVCC SDA/VID1 2 I C TEMP OVERCURRENT VID2 MONITOR DETECT OV C IN 2.6V TO 5.5V VID3 UV OT GATE OV Lo GATE VOUT DRIVE VCC CORE VOUT DAC DRIVE UV & MONITOR LOGIC PHASE ZERO CURRENT + COUT EN DETECT - CMP SOFT ERROR RIPPLE PGND AMP C AMP SS + + FB - - C RP 50 R RING DAMPING CIRCUIT R RP C C C GND VOUT R COMP FIGURE 2. FUNCTIONAL BLOCK DIAGRAM FN9171 Rev 2.00 Page 2 of 17 August 10, 2015