Datasheet Cover Renesas RA6M2 Group 32 Datasheet 32-Bit MCU Renesas Advanced (RA) Family Renesas RA6 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (RA6M2 Group Datasheet Leading performance 120-MHz Arm Cortex -M4 core, up to 1-MB code flash memory, 384-KB SRAM, Capacitive Touch Sensing Unit, Ethernet MAC Controller, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog. Features Arm Cortex-M4 Core with Floating Point Unit (FPU) System and Power Management Armv7E-M architecture with DSP instruction set Low power modes Maximum operating frequency: 120 MHz Realtime Clock (RTC) with calendar and VBATT support Support for 4-GB address space Event Link Controller (ELC) On-chip debugging system: JTAG, SWD, and ETM DMA Controller (DMAC) 8 Boundary scan and Arm Memory Protection Unit (Arm MPU) Data Transfer Controller (DTC) Key Interrupt Function (KINT) Memory Power-on reset Up to 1-MB code flash memory (40 MHz zero wait states) Low Voltage Detection (LVD) with voltage settings 32-KB data flash memory (125,000 erase/write cycles) Security and Encryption Up to 384-KB SRAM Flash Cache (FCACHE) AES128/192/256 Memory Protection Units (MPU) 3DES/ARC4 Memory Mirror Function (MMF) SHA1/SHA224/SHA256/MD5 128-bit unique ID GHASH RSA/DSA/ECC Connectivity True Random Number Generator (TRNG) Ethernet MAC Controller (ETHERC) Human Machine Interface (HMI) Ethernet DMA Controller (EDMAC) USB 2.0 Full-Speed (USBFS) module Capacitive Touch Sensing Unit (CTSU) - On-chip transceiver Parallel Data Capture Unit (PDC) Serial Communications Interface (SCI) with FIFO 10 Multiple Clock Sources Serial Peripheral Interface (SPI) 2 Main clock oscillator (MOSC) (8 to 24 MHz) 2 I C bus interface (IIC) 3 Sub-clock oscillator (SOSC) (32.768 kHz) Controller Area Network (CAN) 2 High-speed on-chip oscillator (HOCO) (16/18/20 MHz) Serial Sound Interface Enhanced (SSIE) Middle-speed on-chip oscillator (MOCO) (8 MHz) SD/MMC Host Interface (SDHI) 2 Low-speed on-chip oscillator (LOCO) (32.768 kHz) Quad Serial Peripheral Interface (QSPI) IWDT-dedicated on-chip oscillator (15 kHz) IrDA interface Clock trim function for HOCO/MOCO/LOCO Sampling Rate Converter (SRC) Clock out support External address space General-Purpose I/O Ports - 8-bit or 16-bit bus space is selectable per area - SDRAM support Up to 110 input/output pins - Up to 1 CMOS input Analog - Up to 109 CMOS input/output 12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits - Up to 21 input/output 5 V tolerant each 2 - Up to 18 high current (20 mA) 12-bit D/A Converter (DAC12) 2 Operating Voltage High-Speed Analog Comparator (ACMPHS) 6 Temperature Sensor (TSN) VCC: 2.7 to 3.6 V Timers Operating Temperature and Packages General PWM Timer 32-bit Enhanced High Resolution Ta = -40C to +105C (GPT32EH) 4 - 145-pin LGA (7 mm 7 mm, 0.5 mm pitch) General PWM Timer 32-bit Enhanced (GPT32E) 4 - 144-pin LQFP (20 mm 20 mm, 0.5 mm pitch) General PWM Timer 32-bit (GPT32) 6 - 100-pin LQFP (14 mm 14 mm, 0.5 mm pitch) Asynchronous General-Purpose Timer (AGT) 2 Watchdog Timer (WDT) Safety Error Correction Code (ECC) in SRAM SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access R01DS0357EJ0110 Rev.1.10 Page 2 of 100 May 14, 2021