C8051F502-IMR

C8051F50x/F51x Mixed Signal ISP Flash MCU Family Analog Peripherals Memory - 12-Bit ADC - 4352 bytes internal data RAM (256 + 4096 XRAM) Up to 200 ksps - 64 or 32 kB Flash In-system programmable in Up to 32 external single-ended inputs 512-byte Sectors VREF from on-chip VREF, external pin or V DD Digital Peripherals Internal or external start of conversion source Built-in temperature sensor - 40, 33, or 25 Port I/O All 5 V tolerant - Two Comparators - CAN 2.0 Controllerno crystal required Programmable hysteresis and response time - LIN 2.1 Controller (Master and Slave capable) no Configurable as interrupt or reset source Low current crystal required On-Chip Debug - Hardware enhanced UART, SMBus, and - On-chip debug circuitry facilitates full speed, non- enhanced SPI serial ports intrusive in-system debug (no emulator required) - Four general purpose 16-bit counter/timers - Provides breakpoints, single stepping, - 16-Bit programmable counter array (PCA) with six inspect/modify memory and registers capture/compare modules and enhanced PWM - Superior performance to emulation systems using functionality ICE-chips, target pods, and sockets Clock Sources - Low cost, complete development kit - Internal 24 MHz with 0.5% accuracy for CAN and Supply Voltage 1.8 to 5.25 V master LIN operation - Typical operating current: 19 mA at 50 MHz - External oscillator: Crystal, RC, C, or clock - Typical stop mode current: 2 A (1 or 2 pin modes) High-Speed 8051 C Core - Can switch between clock sources on-the-fly - Pipelined instruction architecture executes 70% of useful in power saving modes instructions in 1 or 2 system clocks Packages - Up to 50 MIPS throughput with 50 MHz clock - 48-Pin QFP/QFN (C8051F500/1/4/5) - Expanded interrupt handler - 40-Pin QFN (C8051F508/9-F510/1) - 32-Pin QFP/QFN (C8051F502/3/6/7) Automotive Qualified - Temperature Range: 40 to +125 C - Compliant to AEC-Q100 ANALOG DIGITAL I/O PERIPHERALS UART 0 Ports 0-4 A 12-bit TEMP M Crossbar SMBus 200 ksps SENSOR U SPI External ADC X Memory PCA Interface Timers 0-3 CAN VREG Voltage LIN Comparators 0-1 VREF 24 MHz PRECISION 2x Clock Multiplier INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 64 kB 8051 CPU 4 kB XRAM ISP FLASH (50 MIPS) FLEXIBLE DEBUG POR WDT INTERRUPTS CIRCUITRY Rev. 1.2 3/11 Copyright 2011 by Silicon Laboratories C8051F500/1/2/3/4/5/6/7/8/9-F510/1C8051F50x/F51x 2 Rev. 1.2