Si5316-EVB Si5319-EVB Si5322/23-EVB Si5324-EVB Si5325/26-EVB Si5327-EVB Si5316, Si5319, Si5322/23, Si5324, Si5325/26, AND Si5327 EVB USERS GUIDE 1. Introduction The Si5316-EVB, Si5319-EVB, Si5322/23-EVB, Si5324-EVB, Si5325/26-EVB, and Si5327-EVB provide platforms for evaluating Silicon Laboratories Si5316, Si5319, Si5322/Si5323, Si5324, Si5325/Si5326, and Si5327 Any-Frequency Precision Clock Timing ICs. The Si5316, Si5322, and Si5323 are controlled directly using configuration pins on the devices, while the Si5319, Si5324, Si5325, Si5326, and Si5327 are controlled by a 2 microprocessor or MCU (micro-controller unit) via an I C or SPI interface. The Si5316 is a jitter attenuator with a loop bandwidth ranging from 60 Hz to 8.4 kHz. The Si5322 and Si5325 are low jitter clock multipliers with a loop bandwidth ranging from 30 kHz to 1.3 MHz. The Si5319, Si5323, and Si5326 are jitter-attenuating clock multipliers, with a loop bandwidth ranging from 60 Hz to 8.4 kHz. The Si5324 and Si5327 have features and capabilities very similar to the Si5326, but they have much lower loop bandwidths that range from 4 to 525 Hz. The Si5326 device can optionally be configured to operate as a Si5325, so a single evaluation board is available to evaluate both devices. Likewise, the Si5323 can be configured to operate as a Si5322, so the two devices share a single evaluation board. The Si531x/2x Any-Frequency Precision Clocks are based on Silicon Laboratories third-generation DSPLL technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The devices have excellent phase noise and jitter performance. The Si5316 is a jitter attenuator that supports jitter generation of 0.3 ps RMS (typ) across the 12 kHz20 MHz and 50 kHz80 MHz jitter filter bandwidths. The Si5319, Si5323, and Si5326 jitter attenuating clock multipliers support jitter generation of 0.3 ps RMS (typ) across the 12 kHz20 MHz and 50 kHz80 MHz jitter filter bandwidths. The Si5324 and Si5327 are jitter attenuating clock multipliers supporting jitter attenuation of 0.3 ps RMS (typ) and 0.5 ps RMS (typ) across the 12 kHz to 20 MHz and 50 kHz to 80 MHz bands. The Si5322 and Si5325 support jitter generation of 0.6 ps RMS (typ) across the 12 kHz20 MHz and 50 kHz80 MHz jitter filter bandwidths. For all devices, the DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. These devices are ideal for providing clock multiplication/clock division, jitter attenuation, and clock distribution in mid-range and high-performance timing applications. Figure 1. Si532x QFN EVB Rev. 0.6 1/12 Copyright 2012 by Silicon Labs Si531x/2x-EVBSi531x-EVB Si532x-EVB Table 1. Features by Part Number Any-Frequency Precision Clock Multipliers Si5322 2 2 Pin 15 to 19 to 0.6 ps 30 kHz1.3 MHz Y N LOS 6 x 6 707 1050 rms typ 36-QFN 2 Si5325 2 2 I C or 10 to 10 to 0.6 ps 30 kHz1.3 MHz Y N LOS, FOS 6 x 6 SPI 710 1400 rms typ 36-QFN Any-Frequency Precision Clock Multipliers with Jitter Attenuation Si5316 2 1 Pin 19 to 19 to 0.3 ps 60 Hz8.4 kHz N N LOL, LOS 6 x 6 710 710 rms typ 36-QFN 2 Si5319 1 1 I C or .002 to .002 to 0.3 ps 60 Hz8.4 kHz Y N LOL, LOS 6 x 6 SPI 710 1400 rms typ 36-QFN Si5323 2 2 Pin .008 to .008 to 0.3 ps 60 Hz8.4 kHz Y Y LOL, LOS 6 x 6 707 1050 rms typ 36-QFN 2 Si5324 2 2 I C or .002 to .002 to 0.3 ps 4525 Hz Y Y LOL, LOS, 6x6 SPI 710 1400 rms typ FOS 36-QFN 2 Si5326 2 2 I C or .002 to .002 to 0.3 ps 60 Hz8.4 kHz Y Y LOL, LOS, 6x6 SPI 710 1400 rms typ FOS 36-QFN 2 Si5327 2 2 I C or .002 to .002 to 0.5 ps 4525 Hz Y Y LOL, LOS 6 x 6 SPI 710 808 rms typ 36-QFN 2. Applications The Si531x/2x Any-Frequency Precision Clocks have a comprehensive feature set, including any-frequency synthesis, multiple clock inputs, multiple clock outputs, alarm and status outputs, hitless switching between input clocks, programmable output clock signal format (LVPECL, LVDS, CML, CMOS), output phase adjustment between output clocks, and output phase adjustment between all output clocks and the selected reference input clock (phase increment/decrement). For more details, consult the Silicon Laboratories timing products website at www.silabs.com/timing. All six evaluation boards (EVBs) have an MCU (C8051F340) that support USB communications with a PC host. For the pin controlled parts (Si5316, Si5322, and Si5323), the pin settings of the devices are determined by the MCU and the PC resident software that is provided with the EVB. For the MCU controlled parts (Si5319, Si5324, 2 Si5325, Si5326, and Si5327), the devices are controlled and monitored through the serial port (either SPI or I C). A CPLD sits between the MCU and the Any-Frequency Precision Clock device that performs voltage level translation and stores the pin configuration data for the pin controlled devices. Jumper plugs are provided so that the user can bypass the MCU/CPLD to manually control the pin controlled devices. Ribbon headers and SMA connectors are included so that external clock in, clock out, and status pins can be easily accessed by the user. For the MCU controlled devices (Si5319, Si5324, Si5325, Si5326, and Si5327), the user also has the option of bypassing the MCU and controlling the parts from an external serial device. On-board termination is included so that the user can evaluate single-ended or differential as well as ac or dc coupled clock inputs and outputs. A separate DUT (Device Under Test) power supply connector is included so that the Any-Frequency Precision Clocks can be run at either 1.8, 2.5 or 3.3 V, while the USB MCU remains at 3.3 V. LEDs are provided for convenient monitoring of key status signals. 2 Rev. 0.6 Device PN Clock Inputs Clock Outputs Control Input Freq (MHz) Output Freq (MHz) Jitter Generation (12 kHz20 MHz) Prog. Loop BW Clock Mult. Hitless Switching Alarms Package