74LCX541MTR STMicroelectronics

74LCX541 Low voltage CMOS octal bus buffer (3-state) with 5V tolerant inputs and outputs Features 5V tolerant inputs and outputs High speed: t = 8.0ns (Max) at V = 3V PD CC Power down protection on inputs and outputs Symmetrical output impedance: SO-20 TSSOP20 I = I = 24mA (Min) at V = 3V OH OL CC PCI bus levels guaranteed at 24mA Balanced propagation delays: Description t t PLH PHL The 74LCX541 is a low voltage CMOS octal bus Operating voltage range: buffer (non-inverted) fabricated with sub-micron V (Opr) = 2.0V to 3.6V 2 CC silicon gate and double-layer metal wiring C MOS Pin and function compatible with technology. It is ideal for low power and high 74 series 541 speed 3.3V applications it can be interfaced to 5V signal environment for both inputs and Latch-up performance exceeds outputs. 500mA (JESD 17) The 3 STATE control gate operates as two input ESD performance: AND such that if either G1 and G2 are high, all HBM > 2000V eight outputs are in the high impedance state. In (MIL STD 883 method 3015) MM > 200V order to enhance PC board layout the 74LCX541 offers a pinout having inputs and outputs on opposite sides of the package. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Order codes Part number Package Packaging 74LCX541MTR SO-20 Tape and reel 74LCX541TTR TSSOP20 Tape and reel January 2007 Rev 5 1/17 www.st.com 17Contents 74LCX541 Contents 1 Logic symbols and I/O equivalent circuit 3 2 Pin settings 4 2.1 Pin connection 4 2.2 Pin description 4 3 Logic states 5 3.1 Truth table 5 4 Maximum rating . 6 4.1 Recommended operating conditions . 6 5 Electrical characteristics . 7 6 Test circuit . 9 7 Waveforms 10 8 Package mechanical data 11 9 Revision history . 16 2/17