74LCX573 OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: t = 8.0 ns (MAX.) at V = 3V PD CC POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: SOP TSSOP I = I = 24mA (MIN) at V = 3V OH OL CC PCI BUS LEVELS GUARANTEED AT 24 mA Table 1: Order Codes BALANCED PROPAGATION DELAYS: t t PLH PHL PACKAGE T & R OPERATING VOLTAGE RANGE: V (OPR) = 2.0V to 3.6V (1.5V Data SOP 74LCX573MTR CC Retention) TSSOP 74LCX573TTR PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 enable input (LE) and an output enable input (OE). LATCH-UP PERFORMANCE EXCEEDS While the LE inputs is held at a high level, the Q 500mA (JESD 17) outputs will follow the data input. When the LE is ESD PERFORMANCE: taken low, the Q outputs will be latched at the logic HBM > 2000V (MIL STD 883 method 3015) level of D input data. While the (OE) input is low, MM > 200V the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the DESCRIPTION outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V The 74LCX573 is a low voltage CMOS OCTAL AC/ACT family, combined with a lower power D-TYPE LATCH with 3 STATE OUTPUT consumption. NON-INVERTING fabricated with sub-micron 2 All inputs and outputs are equipped with silicon gate and double-layer metal wiring C MOS protection circuits against static discharge, giving technology. It is ideal for low power and high them 2KV ESD immunity and transient excess speed 3.3V applications it can be interfaced to 5V voltage. signal environment for both inputs and outputs. These 8 bit D-Type latch are controlled by a latch Figure 1: Pin Connection And IEC Logic Symbols Rev. 5 September 2004 1/13 Obsolete Product(s) - Obsolete Product(s)74LCX573 Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description Table 3: Truth Table PIN N SYMBOL NAME AND FUNCTION INPUT OUTPUT 1OE 3 State Output Enable OE LE D Q Input (Active LOW) HXX Z 2, 3, 4, 5, 6, D0 to D7 Data Inputs L L X NO CHANGE* 7, 8, 9 LHL L 12, 13, 14, Q0 to Q7 3-State Latch Outputs 15, 16, 17, LH H H 18, 19 X : Dont Care 11 LE Latch Enable Input Z : High Impedance 10 GND Ground (0V) * : Q Outputs are latched at the time when the LE input is taken 20 V Positive Supply Voltage CC LOW. Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 Obsolete Product(s) - Obsolete Product(s)