74LCX74MTR STMicroelectronics

74LCX74 Low voltage CMOS dual D-Type Flip Flop with 5V tolerant inputs Features 5V tolerant inputs High speed: f = 150MHz (Max) at V = 3V MAX CC Power down protection on inputs and outputs Symmetrical output impedance: SO-14 TSSOP14 I = I = 24mA (Min) at V = 3V OH OL CC PCI bus levels guaranteed at 24mA Description Balanced propagation delays: t t The 74LCX74 is a low voltage CMOS dual D-type PLH PHL flip flop with preset and clear non inverting Operating voltage range: fabricated with sub-micron silicon gate and V (Opr) = 2.0V to 3.6V 2 CC double-layer metal wiring C MOS technology. It is Pin and function compatible with ideal for low power and high speed 3.3V 74 series 74 applications it can be interfaced to 5V signal environment for inputs. Latch-up performance exceeds 500mA (JESD 17) A signal on the D INPUT is transferred to the Q ESD performance: OUTPUT during the positive going transition of the clock pulse. HBM > 2000V (MIL STD 883 method 3015) MM > 200V CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Order codes Part number Package Packaging 74LCX74MTR SO-14 Tape and reel 74LCX74TTR TSSOP14 Tape and reel July 2006 Rev 8 1/17 www.st.com 17 Obsolete Product(s) - Obsolete Product(s)Contents 74LCX74 Contents 1 Logic symbols and I/O equivalent circuit 3 1.1 Logic diagram . 3 2 Pin settings 4 2.1 Pin connection 4 2.2 Pin description 4 2.3 Truth table 4 3 Maximum rating . 5 3.1 Recommended operating conditions . 5 4 Electrical characteristics . 6 5 Test circuit . 8 6 Waveforms . 8 7 Package mechanical data 11 8 Revision history . 16 2/17 Obsolete Product(s) - Obsolete Product(s)