74LVC374A OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE 5V TOLERANT INPUTS HIGH SPEED: t = 6.8ns (MAX.) at V = 3V PD CC POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: I = I = 24mA (MIN) at V = 3V OH OL CC SOP TSSOP PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: t t PLH PHL Table 1: Order Codes OPERATING VOLTAGE RANGE: V (OPR) = 1.65V to 3.6V (1.2V Data PACKAGE T & R CC Retention) SOP 74LVC374AMTR PIN AND FUNCTION COMPATIBLE WITH TSSOP 74LVC374ATTR 74 SERIES 374 LATCH-UP PERFORMANCE EXCEEDS While the (OE) input is low, the 8 outputs will be in 500mA (JESD 17) a normal logic state (high or low logic level) and ESD PERFORMANCE: while high level the outputs will be in a high HBM > 2000V (MIL STD 883 method 3015) impedance state. MM > 200V The Output control does not affect the internal operation of flip flops that is, the old data can be DESCRIPTION retained or the new data can be entered even The 74LVC374A is an advanced high-speed while the outputs are off. Power down protection is CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE provided on all inputs and 0 to 7V can be accepted OUTPUTS NON INVERTING fabricated with on inputs with no regard to the supply voltage. sub-micron silicon gate and double-layer metal This device can be used to interface 5V to 3V. 2 wiring C MOS technology. All inputs and outputs are equipped with These 8 bit D-Type latch are controlled by a clock protection circuits against static discharge, giving input (CK) and an output enable input (OE). them 2KV ESD immunity and transient excess On the positive transition of the clock, the Q voltage. outputs will be set to the logic state that were setup at the D inputs. Figure 1: Pin Connection And IEC Logic Symbols Rev. 2 July 2004 1/14 Obsolete Product(s) - Obsolete Product(s)74LVC374A Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW) 2, 5, 6, 9, 12, 15, 16,19 Q0 to Q7 3-State Outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 11 CK Clock 10 GND Ground (0V) 20 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUT OE CK D Q HX X Z L X NO CHANGE LLL LHH X : Dont Care Z :High Impedance 2/14 Obsolete Product(s) - Obsolete Product(s)