74LVX594 LOW VOLTAGE CMOS 8 BIT SHIFT REGISTER WITH OUTPUT REGISTER (5V TOLERANT INPUTS) HIGH SPEED: t = 5.5ns (TYP.) at V = 3.3V PD CC 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: V =0.8V, V =2V at V =3V IL IH CC LOW POWER DISSIPATION: SOP TSSOP I = 4 A (MAX.) at T =25C CC A LOW NOISE: V = 0.3V (TYP.) at V = 3.3V OLP CC Table 1: Order Codes SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) PACKAGE T & R OH OL BALANCED PROPAGATION DELAYS: SOP 74LVX594MTR t t PLH PHL TSSOP 74LVX594TTR OPERATING VOLTAGE RANGE: V (OPR) = 2V to 3.6V (1.2V Data Retention) CC register and the storage register. A serial (QH) PIN AND FUNCTION COMPATIBLE WITH output is provided for cascading purposes. Both 74 SERIES 594 the shift register and storage register use IMPROVED LATCH-UP IMMUNITY positive-edge triggered clocks. If the clocks are POWER DOWN PROTECTION ON INPUTS connected together, the shift register state will always be one clock pulse ahead of the storage DESCRIPTION register. The 74LVX594 is a low voltage CMOS 8 BIT Power down protection is provided on all inputs SHIFT REGISTER WITH OUTPUT REGISTER and 0 to 7V can be accepted on inputs with no fabricated with sub-micron silicon gate and regard to the supply voltage. This device can be 2 double-layer metal wiring C MOS technology. It is used to interface 5V to 3V system. It combines ideal for low power, battery operated and low high speed performance with the true CMOS low noise 3.3V applications. power consumption. This device contains an 8-bit serial-in, parallel-out All inputs and outputs are equipped with shift register that feeds an 8-bit D-type storage protection circuits against static discharge, giving register. Separate clocks and direct overriding them 2KV ESD immunity and transient excess clear (SCLR, RCLR) are provided for both the shift voltage. Figure 1: Pin Connection And IEC Logic Symbols Rev. 5 August 2004 1/1474LVX594 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, QA to QH Data Outputs 6, 7, 15 9 QH Serial Data Output 10 SCLR Shift Register Clear Input 11 SCK Shift Register Clock Input 13 RCLR Storage Register Clear Input 14 SI Serial Data Input 12 RCK Storage Register Clock Input 8 GND Ground (0V) 16 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUTS SI SCK SCLR RCK RCLR X X L X X SHIFT REGISTER IS CLEAR FIRST STAGE OF SHIFT REGISTER GOES LOW LHXX OTHER STAGES STORE THE DATA OF PREVI- OUS STAGE, RESPECTIVELY FIRST STAGE OF SHIFT REGISTER GOES HIGH HHXX OTHER STAGES STORE THE DATA OF PREVI- OUS STAGE, RESPECTIVELY L H X X SHIFT REGISTER STATE IS NOT CHANGED X X X X L STORAGE REGISTER IS CLEARED SHIFT REGISTER DATA IS STORED IN THE XX X H STORAGE REGISTER X X X H STORAGE REGISTER STATE IS NOT CHANGED X : Dont Care 2/14