74VHC574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING HIGH SPEED: f = 180 MHz (TYP.) at V = 5V MAX CC LOW POWER DISSIPATION: I = 4 A (MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28% V (MIN.) NIH NIL CC POWER DOWN PROTECTION ON INPUTS SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 8 mA (MIN) OH OL Table 1: Order Codes BALANCED PROPAGATION DELAYS: t t PLH PHL PACKAGE T & R OPERATING VOLTAGE RANGE: SOP 74VHC574MTR V (OPR) = 2V to 5.5V CC TSSOP 74VHC574TTR PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY while high level the outputs will be in a high impedance state. LOW NOISE: V = 0.9V (MAX.) OLP The Output control does not affect the internal DESCRIPTION operation of flip flop that is, the old data can be The 74VHC574 is an advanced high-speed retained or the new data can be entered even CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE while the outputs are off. OUTPUTS NON INVERTING fabricated with Power down protection is provided on all inputs sub-micron silicon gate and double-layer metal and 0 to 7V can be accepted on inputs with no 2 wiring C MOS technology. regard to the supply voltage. This device can be These 8 bit D-Type flip-flop is controlled by a clock used to interface 5V to 3V. input (CK) and an output enable input (OE). All inputs and outputs are equipped with On the positive transition of the clock, the Q protection circuits against static discharge, giving outputs will be set to the logic states that were them 2KV ESD immunity and transient excess setup at the D inputs. voltage. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and Figure 1: Pin Connection And IEC Logic Symbols Rev. 4 November 2004 1/14 Obsolete Product(s) - Obsolete Product(s)74VHC574 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1OE 3-State Output Enable Input (Active LOW) 2, 3, 4, 5, 6, D0 to D7 Data Inputs 7, 8, 9 12, 13, 14, Q0 to Q7 3-State Outputs 15, 16, 17, 18, 19 11 CK Clock Input (LOW-to-HIGH Edge Triggered) 10 GND Ground (0V) 20 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUT OE CK D Q HX X Z L X NO CHANGE LLL LHH X : Dont Care Z : High Impedance Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/14 Obsolete Product(s) - Obsolete Product(s)