DSM2150F5V DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) FEATURES SUMMARY Glueless Connection to DSP Figure 1. TQFP 80-pin Package Easily add memory, logic, and I/O to the External Port of ADSP-218x, 219x, 2106x, 2116x, 2153x, and TS101 families of DSPs from Analog Devices, Inc. Dual Flash Memories Two independent Flash memory arrays for storing DSP code and data Capable of read-while-write concurrent Flash memory operation Device can be configured as 8-bit or 16-bit Built-in programmable address decoding logic allows mapping individual sectors of each Flash array to any address boundary Each Flash sector can be write protected 512 KByte Main Flash memory TQFP80 (T) Ample storage for boot loading DSP code/ data upon reset and subsequent code swaps Large capacity for storing tables and constants or for data recording 32 KByte Secondary Flash memory Smaller sector size ideal for storing calibration and configuration constants. In-System Programming (ISP) with JTAG Eliminate external serial EEPROM. Program entire chip in 15-35 seconds with Optionally bypass internal DSP boot ROM no involvement of the DSP during start-up and execute code directly Optionally links with DSP JTAG debug from Secondary Flash. Use for custom port start-up code and In-Application Eliminate need for sockets and pre- Programming (IAP). programming of memory and logic Up to 40 Multifunction I/O Pins devices Increase total DSP system I/O capability ISP allows efficient manufacturing and I/O controlled by DSP software or PLD product testing supporting Just-In-Time logic inventory Use low-cost FlashLINK cable with any General purpose PLD PC. Available from www.st.com/psm. Use for peripheral glue logic to keypads, control panel, displays, LCDs, and other Content Security devices Programmable Security Bit blocks access Over 3,000 gates of PLD with 16 macro of device programmers and readers cells Operating Range Eliminate PLDs and external logic devices V : 3.3V 10%, Temp: 40C to +85C CC Create state machines, chip selects, Zero-Power Technology simple shifters and counters, clock 50A standby current typical dividers, delays Flash Memory Speed, Endurance, Retention Simple PSDsoft Express development 120ns, 100K cycles, 15 year retention software, free from www.st.com/psm August 2004 1/73DSM2150F5V TABLE OF CONTENTS FEATURES SUMMARY . 1 SUMMARY DESCRIPTION . 5 PIN DESCRIPTION . 8 ARCHITECTURAL OVERVIEW 10 DSP Address/Data/Control Interface 10 Main Flash Memory 11 Secondary Flash Memory . 11 Programmable Logic (PLDs) 11 Runtime Control Registers 12 Memory Page Register . 12 I/O Ports . 12 JTAG ISP Port 12 Power Management 12 Security and NVM Sector Protection 12 RUNTIME CONTROL REGISTER DEFINITION 13 DETAILED OPERATION 14 Flash Memories . 14 INSTRUCTIONS 19 Reading Flash Memory . 20 Read Memory Contents 20 Read Main Flash Identifier 20 Read Memory Sector Protection Status . 20 Reading the Erase/Program Status Bits . 20 Data Polling Flag (DQ7) . 20 Toggle Flag (DQ6) . 21 Error Flag (DQ5) . 21 Erase Time-out Flag (DQ3) 21 PROGRAMMING FLASH MEMORY . 22 PLDs . 24 Turbo Bit . 24 Decode PLD (DPLD) . 26 Complex PLD (CPLD) 27 Output Macrocell (OMC) 28 Product Term Allocator . 29 Loading and Reading the OMCs . 29 The OMC Mask Register 31 2/73