EVALSTGAP1AS Demonstration board for STGAP1AS galvanically isolated single gate driver Data brief Description The STGAP1AS is a galvanically isolated single gate driver for N-channel MOSFETs and IGBTs with advanced protection, configuration and diagnostic features. The architecture of the STGAP1AS isolates the channel from the control and the low voltage interface circuitry through true galvanic isolation. The EVALSTGAP1AS board allows evaluating all of the STGAP1AS features while driving a power switch with a voltage rating up to 1500 V. Power switches in both TO-220 or TO-247 packages can be evaluated, and the board allows the connection of a heatsink in order to exploit the ability of the STGAP1AS to handle very high power applications. Features In combination with the STEVAL-PCC009V2 High voltage rail up to 1500 V communication board and the STGAP1AS 5 A sink/source driver current capability evaluation software, the board allows to easily 5 A active Miller clamp enable, configure or disable all of the drivers protection and control features through the SPI Gate driving voltage up to 36 V interface. Advanced diagnostic is also available Negative gate driving ability thanks to the drivers status registers that can be Desaturation detection accessed through the SPI. Overcurrent protection Multiple boards can be connected together and share the same logic supply voltage and control Output 2-level turn-off (2LTO) UVLO on each signals in order to evaluate half-bridge, supply voltage interleaved or even more complex topologies. Overtemperature warning and shut-down The board allows implementing the SPI daisy protection chain when more than one device is used. 3.3/5 V logic input interface Optimized reference layout SPI with daisy chain feature for parameters programming and diagnostic Suitable to be used in combination with STEVAL-PCC009V2 and configuration GUI Fault LED indicators RoHS compliant November 2016 DocID029958 Rev 1 1/8 For further information contact your local STMicroelectronics sales office. www.st.com X 9 & - 23(1 -3 ,13 ,13 ,10 , * BUHPRWH , * 73 &. &6 6 ,13 9 ,10 , * 6 2 ,10 , * ,13BUHPRWH 6 , - 23(1 -3 9 6 2BSL 6 2 &/26( -3 ,10 , * BUHPRWH ,10 , * 95(* 9 6 2 , * &. &. &6 23(1 -3 6 , 6 ,13BUHPRWH &6 6 2 ,10 , * BUHPRWH 9 6 6 2BSL , * 6 2BSL , * 6 - ,13 9 ,10 , * - - /RZ YROWDJH +LJK YROWDJH X 9 & 9/ 73 9+ *1 B,62 - 73 9/ X 9 9+ 9/ 9/ & 9+ 73 Schematic diagrams EVALSTGAP1AS Schematic diagrams Figure 1. EVALSTGAP1AS circuit schematic connectors and configuration jumpers 0 Q & Q Q X 9 6 2 9(6/ 0 67(5 & Q 9 95(*B,62 & Q 9 9 & 23(1 X 9 -3 9 9UHJ & & 9 X 9 Q 9/ *1 LVR &/26( -3 & 9/ & Q 9 9 X & & 9 Q Q 9 L/&. 9 9 2/8 DocID029958 Rev 1 9+ 9/ *1 L 9/ 9+ 9 9 *1