HCF4098B DUAL MONOSTABLE MULTIVIBRATOR RETRIGGERABLE/RESETTABLE CAPABILITY TRIGGER AND RESET PROPAGATION DELAYS INDEPENDENT OF R , C X X TRIGGERING FROM LEADING OR TRAILING EDGE DIP SOP Q AND Q BUFFERED OUTPUT AVAILABLE SEPARATE RESETS WIDE RANGE OF OUTPUT PULSE WIDTHS QUIESCENT CURRENT SPECIFIED UP TO ORDER CODES 20V PACKAGE TUBE T & R 5V, 10V AND 15V PARAMETRIC RATINGS DIP HCF4098BEY INPUT LEAKAGE CURRENT SOP HCF4098BM1 HCF4098M013TR I = 100nA (MAX) AT V = 18V T = 25C I DD A 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC wide range of output pulse widths from the Q and JESD13B STANDARD SPECIFICATIONS Q terminals. The time delay from trigger input to FOR DESCRIPTION OF B SERIES CMOS output transition (trigger propagation delay) and DEVICE the time delay from reset input to output transition (reset propagation delay) and the time delay from DESCRIPTION reset input to output transition (reset propagation The HCF4098B is a monolithic integrated circuit delay) are independent of R and C . Leading X X fabricated in Metal Oxide Semiconductor edge triggering (+TR) and trailing edge triggering technology available in DIP and SOP packages. (-TR) inputs are provided for triggering from either The HCF4098B dual precision monostable edge of an input pulse. An unused +TR input multivibrator provides stable retriggerable/ should be tied to V . An unused -TR input should SS resettable one-shot operation for any fixed voltage be tied to V . A RESET (on low level) is provided DD timing application. An external resistor (R ) and X for immediate termination of the output pulse or to an external capacitor (C ) control the timing for X prevent output pulses when power is turned on. the circuit. Adjustment of R and C provides a X X PIN CONNECTION September 2001 1/10HCF4098B An unused RESET input should be tied to V . multivibrator can be calculated by : T = 1/2 R C DD X X However, if an entire section of the HCF4098B is for C > 0.01F. The min. value of external X not used, its reset should be tied to V (see table resistance, R , is 5K. The max. values of SS X 1). In normal operation the circuit triggers (extends external capacitance, C , is 100 F. The output X the output pulse one period) on the application of pulse width has variations of 2.5% typically, over each new trigger pulse. For operation in the the temperature range of -55 C to 125 C for non-retiggerable mode, Q is connected to -TR C =1000pF and R = 100K . For power supply X X when leading edge triggering (+TR) is used or Q is variation of 5% typically , for V = 10V and 15V DD connected to +TR when trailing edge triggering and 1% typically for V = 5V at C = 1000pF DD X (-TR) is used. The time period (T) for this and R = 5K . X IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 4, 12 +TR Leading Trigger Inputs 5, 11 -TR Trailing Trigger Inputs 3, 13 RESET Reset Inputs 1, 15 C 1, C 2 External Capacitors X X R C 1 X X 2, 14 External resistors to Vdd R C 2 X X 6, 7 Q1, Q1 Ouputs Mono 1 10, 9 Q2, Q2 Outputs Mono 2 V 8 Negative Supply Voltage SS 16 V Positive Supply Voltage DD FUNCTIONAL DIAGRAM 2/10