L9374TRLF STMicroelectronics

L9374LF Four channel valve driver Datasheet - production data 16 bit serial peripheral interface, up to 5 MHz with diagnosis Battery compatible supply voltage Detailed load diagnosis Over load protection Open load (off-state) 0 03 Undercurrent PowerSO-36 Undervoltage Temperature warning and shutdown Power or signal GND loss Freewheeling diode loss Silent valve driver test Features Description Four protected low-side drivers with diagnostics The L9374LF is a SPI (serial peripheral interface) controlled four channel low side driver with Two 140 m PWM controlled outputs integrated recirculation diodes. (Q1 & Q2) Two 250 m current controlled outputs with The output duty cycle (all channels) / current 6 % accuracy (Q3 & Q4) regulation level (Q3 & Q4 only) can be programmed individually. It is possible to program All outputs with 35 V Zener Clamp two consecutive output duty cycles or target Programmable output timer currents per channel as well as an individual Clock monitor duration time for each channel actuation. Integrated recirculation diodes . Table 1. Device summary Order code Package Packing L9374LF PowerSO-36 Tube L9374TRLF PowerSO-36 Tape and reel October 2013 DocID025414 Rev 1 1/80 This is information on a product in full production. www.st.comContents L9374LF Contents 1 Block diagram 8 2 Pins description 9 3 Electrical specifications . 11 3.1 Absolute maximum ratings 11 3.2 ESD susceptibility . 12 3.2.1 HBM 12 3.2.2 MM . 12 3.3 Electrical characteristics 12 3.3.1 Supply current 12 3.3.2 Output power stages . 12 3.3.3 Freewheeling diode 14 3.3.4 Output timing characteristics . 14 3.3.5 PWM output behavior 15 3.3.6 Q3 / Q4 (current controller) 16 3.3.7 Logic inputs / outputs . 16 3.3.8 Logic outputs (MISO) . 17 3.3.9 Diagnostic functions at output stage . 17 3.3.10 General diagnostic functions . 18 3.3.11 Filtering times 18 3.3.12 VD measurement 19 3.3.13 Rs measurement 19 3.3.14 V FWD measurement 20 3.3.15 Internal oscillator 20 3.3.16 SPI timing characteristics SPICLK, MISO, MOSI, SPICS . 20 4 Circuit description 22 4.1 SPI serial peripheral interface . 22 4.1.1 General protocol 23 4.1.2 SPI failure detection 24 4.1.3 Data transfer . 24 4.1.4 Address decoder 25 4.1.5 Parity generator . 25 2/80 DocID025414 Rev 1