M24M02-DRCS6TPK STMicroelectronics

M24M02-DR M24M02-R 2-Mbit serial IC bus EEPROM Datasheet - production data Features 2 Compatible with all I C bus modes: 1 MHz 400 kHz 100 kHz SO8 (MN) 150 mil width Memory array: 2 Mbit (256 Kbyte) of EEPROM Page size: 256 byte Additional Write lockable page (M24M02- DR order codes) Single supply voltage: WLCSP 1.8 V to 5.5 V over 40 C / +85 C Write: Byte Write within 10 ms Page Write within 10 ms Random and sequential Read modes Write protect of the whole memory array Unsawn wafer Enhanced ESD/Latch-Up protection More than 4 million Write cycles More than 200-years data retention Packages SO8 ECOPACK2 WLCSP ECOPACK2 Unsawn wafer (each die is tested) RoHS compliant and halogen-free (ECOPACK2 ) January 2018 DocID18204 Rev 10 1/40 This is information on a product in full production. www.st.comContents M24M02-DR M24M02-R Contents 1 Description . 6 2 Signal description . 8 2.1 Serial Clock (SCL) . 8 2.2 Serial Data (SDA) 8 2.3 Chip Enable (E2) 8 2.4 Write Control (WC) . 8 2.5 V (ground) . 8 SS 2.6 Supply voltage (V ) . 9 CC 2.6.1 Operating supply voltage (V ) 9 CC 2.6.2 Power-up conditions 9 2.6.3 Device reset . 9 2.6.4 Power-down conditions 9 3 Memory organization . 10 4 Device operation . 11 4.1 Start condition 12 4.2 Stop condition 12 4.3 Data input . 12 4.4 Acknowledge bit (ACK) 12 4.5 Device addressing 13 5 Instructions . 14 5.1 Write operations 14 5.1.1 Byte Write . 15 5.1.2 Page Write . 16 5.1.3 Write Identification Page (M24M02-DR only) . 17 5.1.4 Lock Identification Page (M24M02-DR only) . 17 5.1.5 ECC (Error Correction Code) and Write cycling 17 5.1.6 Minimizing Write delays by polling on ACK 18 5.2 Read operations 19 5.2.1 Random Address Read . 20 2/40 DocID18204 Rev 10