M48T35 M48T35Y 5 V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM Features Integrated, ultra low power SRAM, real-time clock, power-fail control circuit and battery BYTEWIDE RAM-like clock access BCD coded year, month, day, date, hours, 28 minutes, and seconds 1 Frequency test output for real-time clock Automatic power-fail chip deselect and WRITE PCDIP28 protection Battery/crystal CAPHAT WRITE protect voltages V = power-fail deselect voltage): PFD M48T35: V = 4.75 to 5.5 V CC 4.5 V V 4.75 V PFD SNAPHAT M48T35Y: V = 4.5 to 5.5 V CC Battery/crystal 4.2 V V 4.5 V PFD Self-contained battery and crystal in the CAPHAT DIP package SOIC package provides direct connection for a SNAPHAT housing containing the battery and crystal SNAPHAT housing (battery and crystal) is 28 replaceable 1 Pin and function compatible with JEDEC standard 32 Kb x 8 SRAMs SOH28 RoHS compliant Lead-free second level interconnect June 2011 Doc ID 2611 Rev 10 1/28 www.st.com 1Contents M48T35, M48T35Y Contents 1 Description . 5 2 Operation modes 8 2.1 READ mode 8 2.2 WRITE mode 10 2.3 Data retention mode . 11 3 Clock operations . 12 3.1 Reading the clock . 12 3.2 Setting the clock 12 3.3 Stopping and starting the oscillator . 12 3.4 Calibrating the clock . 13 3.5 Century bit 14 3.6 V noise and negative going transients . 16 CC 4 Maximum ratings . 17 5 DC and AC parameters 18 6 Package mechanical data 21 7 Part numbering 25 8 Environmental information . 26 9 Revision history . 27 2/28 Doc ID 2611 Rev 10