M74HC175 QUAD D-TYPE FLIP FLOP WITH CLEAR HIGH SPEED : t = 16 ns (TYP.) at V = 6V PD CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC175B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC175M1R M74HC175RM13TR 74 SERIES 175 TSSOP M74HC175TTR DESCRIPTION The M74HC175 is an high speed CMOS HEX 4Q) on the positive-going edge of the clock pulse. D-TYPE FLIP FLOP WITH CLEAR fabricated with The reset function is accomplished when the 2 silicon gate C MOS technology. CLEAR input is low and all Q outputs are low These four flip-flops are controlled by a clock input regardless of other input conditions. (CLOCK) and a clear input (CLEAR). The All inputs are equipped with protection circuits information data applied to the D inputs (1D to 4D) against static discharge and transient excess are transferred to the outputs (1Q to 4Q and 1Q to voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11M74HC175 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Asynchronous Master 1 CLEAR Reset (Active Low) 2, 7, 10, 15 1Q to 4Q Flip-Flop Outputs Complementary Flip-Flop 3, 6, 11, 14 1Q to 4Q Outputs 4, 5, 12, 13 1D to 4D Data Inputs Clock Input (LOW to 9 CLOCK HIGH, edge triggered) 8 GND Ground (0V) 16 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLEAR D CLOCK Q Q LX X L H HL LH HH H L H X Qn Qn NO CHANGE X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11