M74HC4520 DUAL 4 BIT BINARY COUNTER HIGH SPEED : f = 60 MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t PLH PHL ORDER CODES WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC4520B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC4520M1R M74HC4520RM13TR 74 SERIES 4520 TSSOP M74HC4520TTR DESCRIPTION The M74HC4520 is an high speed CMOS DUAL each positive-going transition of the CLOCK. The BINARY COUNTER fabricated with silicon gate counters are cleared by high levels on their clear 2 C MOS technology. lines. It consists of two identical internally synchronous The counter can be cascaded in the ripple mode 4-stage counters. The counter stages are D-TYPE by connecting Q4 to the enable input of the flip-flops having interchangeable CLOCK and subsequent counter while the clock input of the ENABLE inputs for incrementing on either the latter is held permanently low. positive-going or negative-going transition. All inputs are equipped with protection circuits For single-unit operation the ENABLE input is against static discharge and transient excess maintainedhig and the counter advances on voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 Obsolete Product(s) - Obsolete Product(s)M74HC4520 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1CLOCK, Clock Inputs (LOW to 1, 9 2CLOCK HIGH, Edge-Triggered) 2, 10 1CE, 2CE Clock Enable Inputs 3, 4, 5, 6 1Q0 to 1Q3 Data Outputs 1CLEAR, Asynchronous Reset 7, 15 2CLEAR Inputs (Active LOW) 11, 12, 13, 2Q0 tO 2Q3 Data Outputs 14 8 GND Ground (0V) 16 Vcc Positive Supply Voltage TRUTH TABLE INPUTS FUNCTION CLOCK CLOCK ENABLE CLEAR H L INCREMENT COUNTER L L INCREMENT COUNTER X L NO CHANGE X L NO CHANGE L L NO CHANGE H L NO CHANGE X X H Q0 THRU Q3=L X : Dont Care Z : High Impedance 2/12 Obsolete Product(s) - Obsolete Product(s)