SPC570S40E1, SPC570S40E3, SPC570S50E1, SPC570S50E3 32-bit Power Architecture microcontroller for automotive ASILD applications Datasheet - production data Boot time MBIST and LBIST for latent faults Check of safety mechanisms availability and error reaction path functionality by eTQFP100 (14 x 14 x 1.0 mm) eTQFP64 (10 x 10 x 1.0 mm) dedicated mechanisms Safety of the periphery by application-level Features measures supported by replicated peripheral bridges and by LBIST AEC-Q100 qualified Further measures on dedicated peripherals High performance e200z0h dual core (e.g. ADC supervisor) 32-bit Power Architecture technology CPU Junction temperature sensor Core frequency as high as 80 MHz 8-region system memory protection unit Single issue 4-stage pipeline in-order (SMPU) with process ID support (tasks execution core isolation) Variable Length Encoding (VLE) Enhanced SW watchdog Up to 544 KB (512 KB code + 32 KB data, Cyclic redundancy check (CRC) unit suitable for EEPROM emulation) on-chip flash Dual phase-locked loops with stable clock memory: supports read during program and domain for peripherals and FM modulation erase operations, and multiple blocks allowing domain for computational shell EEPROM emulation Nexus Class 3 debug and trace interface Up to 48 KB on-chip general-purpose SRAM Communication interfaces Multi-channel direct memory access controller 2 LINFlexD modules, 3 deserial serial (eDMA paired in lockstep) with 16 channels peripheral interface (DSPI) modules, and Comprehensive new generation ASILD safety Up to 2 FlexCAN interfaces with 32 concept message buffers each Safety of bus masters (core+INTC, DMA) On-chip CAN/UART Bootstrap loader with Boot by delayed lockstep approach Assisted Flash (BAF). Physical Interface (PHY) Safety of storage (Flash, SRAM) by mainly can be ECC UART and CAN Safety of the data path to storage and 2 enhanced 12-bit SAR analog converters periphery by mainly End-to-End EDC (E2E EDC) 1.5 s conversion time (12 MHz) Clock and power, generation and 16 physical channels (fully shared between distribution, supervised by dedicated the 2 SARADC units) monitors Supervisor ADC concept Fault Collection and Control Unit (FCCU) Programmable Cross Triggering Unit (CTU) for collection and reaction to failure Single 3.3 V or 5 V voltage supply notifications 4 general purpose eTimer units (6 channels Memory Error Management Unit (MEMU) each) for collection and reporting of error events Junction temperature range -40 C to 150 C in memories (165 C grade optional) January 2018 DocID024492 Rev 7 1/75 This is information on a product in full production. www.st.comContents SPC570S40Ex, SPC570S50Ex Contents 1 Introduction 6 1.1 Document overview 6 1.2 Description . 6 1.3 Feature overview 9 2 Block diagram . 10 3 Package pinouts and signal descriptions . 14 3.1 Package pinouts 14 3.2 Pin descriptions 16 3.3 Package pads/pins 16 4 Electrical characteristics 22 4.1 Introduction . 22 4.2 Parameter classification 22 4.3 Absolute maximum ratings 23 4.4 Electromagnetic compatibility (EMC) 24 4.5 Electrostatic discharge (ESD) . 24 4.6 Operating conditions 25 4.7 Thermal characteristics 26 4.7.1 Package thermal characteristics 26 4.7.2 Power considerations 27 4.8 Current consumption 30 4.9 I/O pad electrical characteristics . 30 4.9.1 I/O pad types . 30 4.9.2 I/O input DC characteristics 31 4.9.3 I/O output DC characteristics . 33 4.10 RESET electrical characteristics . 38 4.11 Power management electrical characteristics . 41 4.11.1 Voltage regulator electrical characteristics 41 4.12 PMU monitor specifications . 42 4.12.1 Nomenclature 42 2/75 DocID024492 Rev 7