ST10F276Z5T3 STMicroelectronics

ST10F276Z5 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet - production data Features Highly performance 16-bit CPU with DSP functions 31.25 ns instruction cycle time at 64 MHz LQFP144 20 x 20 x 1.4mm max. CPU clock Multiply/accumulate unit (MAC) 16 x 16-bit 4-channel PWM unit + 4-channel XPWM multiplication, 40-bit accumulator A/D converter Enhanced boolean bit manipulations 24-channel 10-bit Single-cycle context switching support 3 s minimum conversion time On-chip memories Serial channels 512 Kbyte Flash memory (32-bit fetch) Two synchronous/asynchronous serial 320 Kbyte extension Flash memory (16-bit channels fetch) Two high-speed synchronous channels Single voltage Flash memories with 2 One I C standard interface erase/program controller and 100 K 2 CAN 2.0B interfaces operating on 1 or 2 CAN erasing/programming cycles. busses (64 or 2x32 message, C-CAN version) Up to 16 Mbyte linear address space for 2 Fail-safe protection code and data (5 Mbytes with CAN or I C) Programmable watchdog timer 2 Kbyte internal RAM (IRAM) Oscillator watchdog 66 Kbyte extension RAM (XRAM) On-chip bootstrap loader External bus Programmable external bus configuration Clock generation and characteristics for different address On-chip PLL with 4 to 12 MHz oscillator ranges Direct or prescaled clock input Five programmable chip-select signals Real-time clock and 32 kHz on-chip oscillator Hold-acknowledge bus arbitration support Up to 111 general purpose I/O lines Interrupt Individually programmable as input, output 8-channel peripheral event controller for or special function single cycle interrupt driven data transfer Programmable threshold (hysteresis) 16-priority-level interrupt system with 56 Idle, Power-down and Standby modes sources, sampling rate down to 15.6ns Single voltage supply: 5 V 10% (embedded Timers: two multi-functional general purpose regulator for 1.8 V core supply) timer units with 5 timers Two 16-channel capture / compare units Table 1. Device summary Order code Package Max. CPU frequency Iflash Xflash RAM Temperature range (C) 40 MHz 512 Kbytes 320 Kbytes 68Kbytes 40 to +125 ST10F276Z5T3 LQFP144 64 MHz 512 Kbytes 320 Kbytes 68Kbytes 40 to +115 February 2017 DocID12448 Rev 3 1/240 This is information on a product in full production. www.st.com Contents ST10F276Z5 Contents 1 Description 14 2 Pin data 17 3 Functional description 24 4 Internal Flash memory 25 4.1 Overview . 25 4.2 Functional description . 25 4.2.1 Structure 25 4.2.2 Modules structure . 26 4.2.3 Low-power mode 28 4.3 Write operation . 28 4.3.1 Power supply drop . 29 4.4 Registers description 29 4.4.1 Flash control register 0 low 29 4.4.2 Flash control register 0 high . 30 4.4.3 Flash control register 1 low 32 4.4.4 Flash control register 1 high . 33 4.4.5 Flash data register 0 low 34 4.4.6 Flash data register 0 high . 34 4.4.7 Flash data register 1 low 35 4.4.8 Flash data register 1 high . 35 4.4.9 Flash address register low . 35 4.4.10 Flash address register high 36 4.4.11 Flash error register 36 4.4.12 XFlash interface control register 37 4.5 Protection strategy 38 4.5.1 Protection registers 38 4.5.2 Flash non volatile write protection X register low 38 4.5.3 Flash non volatile write protection X register high . 39 4.5.4 Flash non volatile write protection I register low 39 4.5.5 Flash non volatile write protection I register high 39 4.5.6 Flash non volatile access protection register 0 . 40 2/240 DocID12448 Rev 3