ST62T01CM3TR

ST6200C ST6201C ST6203C 8-bit MCUs with A/D converter, two timers, oscillator safeguard & safe reset Memories 1K or 2K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out protection 64 bytes RAM Clock, Reset and Supply Management PDIP16 Enhanced reset system Low voltage detector (LVD) for safe Reset Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator (LFAO) SO16 Oscillator safeguard (OSG) 2 Power saving modes: Wait and Stop Interrupt Management 4 interrupt vectors plus NMI and RESET SSOP16 9 external interrupt lines (on 2 vectors) 9 I/O Ports 9 multifunctional bidirectional I/O lines 4 alternate function lines 3 high sink outputs (20mA) 2 Timers Configurable watchdog timer CDIP16W 8-bit timer/counter with a 7-bit prescaler (See Section 11.5 for Ordering Information) Analog Peripheral 8-bit ADC with 4 input channels (except on Development Tools ST6203C) Full hardware/software development package Instruction Set 8-bit data manipulation 40 basic instructions 9 addressing modes Bit manipulation Device Summary Features ST6200C ST6201C ST6203C Program memory - bytes 1K 2K 1K RAM - bytes 64 Operating Supply 3.0V to 6V Analog Inputs 4 - Clock Frequency 8MHz Max Operating Temperature -40C to +125C Packages PDIP16 / SO16 / SSOP16 October 2009 Doc ID 4563 Rev 5 1/100 1Table of Contents ST6200C ST6201C ST6203C . 1 1 INTRODUCTION 6 2 PIN DESCRIPTION 7 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES 8 3.1 MEMORY AND REGISTER MAPS 8 3.1.1 Introduction 8 3.1.2 Program Space 10 3.1.3 Readout Protection . 10 3.1.4 Data Space . 10 3.1.5 Stack Space . 10 3.1.6 Data ROM Window . 12 3.2 PROGRAMMING MODES 14 3.2.1 Program Memory . 14 3.2.2 EPROM Erasing 14 3.3 OPTION BYTES . 15 4 CENTRAL PROCESSING UNIT . 16 4.1 INTRODUCTION . 16 4.2 MAIN FEATURES 16 4.3 CPU REGISTERS 16 5 CLOCKS, SUPPLY AND RESET 18 5.1 CLOCK SYSTEM . 18 5.1.1 Main Oscillator . 19 5.1.2 Oscillator Safeguard (OSG) . 20 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . 21 5.1.4 Register Description . 21 5.2 LOW VOLTAGE DETECTOR (LVD) 22 5.3 RESET . 23 5.3.1 Introduction . 23 5.3.2 RESET Sequence 23 5.3.3 RESET Pin 24 5.3.4 Watchdog Reset . 25 5.3.5 LVD Reset 25 5.4 INTERRUPTS . 26 5.5 INTERRUPT RULES AND PRIORITY MANAGEMENT . 27 5.6 INTERRUPTS AND LOW POWER MODES 27 5.7 NON MASKABLE INTERRUPT 27 5.8 PERIPHERAL INTERRUPTS . 27 5.9 EXTERNAL INTERRUPTS (I/O PORTS) 28 5.9.1 Notes on using External Interrupts .100 . 28 5.10 INTERRUPT HANDLING PROCEDURE . 29 5.10.1Interrupt Response Time . 29 2/100 Doc ID 4563 Rev 5 2