ST72F324K4B6

ST72324Jx ST72324Kx 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE NOT FOR NEW DESIGN Memories 8 to 32K dual voltage High Density Flash (HD- Flash) with read-out protection capability. In- Application Programming and In-Circuit Pro- gramming for HDFlash devices TQFP32 384 to 1K bytes RAM 7 x 7 TQFP44 HDFlash endurance: 100 cycles, data reten- 10 x 10 tion: 20 years at 55C Clock, Reset And Supply Management Enhanced low voltage supervisor (LVD) for main supply with programmable reset thresh- olds and auxiliary voltage detector (AVD) with interrupt capability SDIP32 SDIP42 Clock sources: crystal/ceramic resonator os- 400 mil 600 mil cillators, internal RC oscillator, clock security system and bypass for external clock PLL for 2x frequency multiplication Four Power Saving Modes: Halt, Active-Halt, Wait and Slow 2 Communication Interfaces Interrupt Management SPI synchronous serial interface Nested interrupt controller SCI asynchronous serial interface 10 interrupt vectors plus TRAP and RESET 1 Analog Peripheral (low current coupling) 9/6 external interrupt lines (on 4 vectors) 10-bit ADC with up to 12 robust input ports Up to 32 I/O Ports 32/24 multifunctional bidirectional I/O lines Instruction Set 22/17 alternate function lines 8-bit Data Manipulation 12/10 high sink outputs 63 Basic Instructions 4 Timers 17 main Addressing Modes Main Clock Controller with: Real time base, 8 x 8 Unsigned Multiply Instruction Beep and Clock-out capabilities Configurable watchdog timer 16-bit Timer A with: 1 input capture, 1 output Development Tools compare, external clock input, PWM and Full hardware/software development package pulse generator modes In-Circuit Testing capability 16-bit Timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes Device Summary ST72324J6 ST72324J4 ST72324J2 Features 1 1 1 ST72324K6 ST72324K4 ST72324JK2 Program memory - Flash 32K Flash 16K Flash 8K bytes RAM (stack) - bytes 1024 (256) 512 (256) 384 (256) Voltage Range 3.8V to 5.5V Temp. Range up to -40C to +125C Packages SDIP42, TQFP44 10x10,SDIP32, TQFP32 7x7 1 For new designs in standard and industrial applications, use ST72324B(J/K) order codes, refer to separate datasheet April 2008 Rev. 5 1/164 1Table of Contents 1 INTRODUCTION 7 2 PIN DESCRIPTION 8 3 REGISTER & MEMORY MAP . 13 4 FLASH PROGRAM MEMORY 17 4.1 INTRODUCTION . 17 4.2 MAIN FEATURES 17 4.3 STRUCTURE 17 4.3.1 Read-out Protection 17 4.4 ICC INTERFACE . 18 4.5 ICP (IN-CIRCUIT PROGRAMMING) 19 4.6 IAP (IN-APPLICATION PROGRAMMING) . 19 4.7 RELATED DOCUMENTATION 19 4.7.1 Register Description 19 5 CENTRAL PROCESSING UNIT . 20 5.1 INTRODUCTION . 20 5.2 MAIN FEATURES 20 5.3 CPU REGISTERS 20 6 SUPPLY, RESET AND CLOCK MANAGEMENT 23 6.1 PHASE LOCKED LOOP . 23 6.2 MULTI-OSCILLATOR (MO) . 24 6.3 RESET SEQUENCE MANAGER (RSM) . 25 6.3.1 Introduction . 25 6.3.2 Asynchronous External RESET pin 25 6.3.3 External Power-On RESET 26 6.3.4 Internal Low Voltage Detector (LVD) RESET . 26 6.3.5 Internal Watchdog RESET . 26 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) 27 6.4.1 Low Voltage Detector (LVD) 27 6.4.2 Auxiliary Voltage Detector (AVD) 28 6.4.3 Low Power Modes . 29 6.4.4 Register Description 30 7 INTERRUPTS . 31 7.1 INTRODUCTION . 31 7.2 MASKING AND PROCESSING FLOW 31 7.3 INTERRUPTS AND LOW POWER MODES 33 7.4 CONCURRENT & NESTED MANAGEMENT . 33 7.5 INTERRUPT REGISTER DESCRIPTION 34 7.6 EXTERNAL INTERRUPTS . 36 7.6.1 I/O Port Interrupt Sensitivity 36 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . 38 8 POWER SAVING MODES . 40 8.1 INTRODUCTION . 40 164 8.2 SLOW MODE . 40 8.3 WAIT MODE 41 2/164 2