ST7590

ST7590 Narrow-band OFDM power line networking PRIME compliant system-on-chip Features Fully integrated narrow-band power line networking system-on-chip High performing DSP engine with embedded turn-key firmware for Orthogonal frequency division multiplexing (OFDM) modulation, 41&0 QFN-48 featuring: (7 x 7 mm) 96 sub-carriers in CENELEC A band BDPSK, QDPSK, 8DPSK programmable Suitable for applications compliant with modulations EN50065 and FCC part 15 specifications Programmable bit rate up to 128 kbps -40 C to +85 C temperature range Convolutional coding and Viterbi decoding QFN48 7x7 (ST7590) and TQFP 100 14x14 Signal to noise ratio and channel quality (ST7590T) exposed pad package options estimation Full PRIME compliant PHY Application On chip peripherals: PRIME compliant smart metering and smart grid Host controller UART/SPI interface applications. I2C/SPI external data memory interface High speed SRAM controller for optional Description external SRAM program code execution Watchdog timer ST7590 is the first complete Narrowband OFDM On chip 128 bit AES encryption HW block power line communication system-on-chip made using a multi-power technology with state of the Fully integrated analog front end: art VLSI CMOS lithography. The ST7590 is based ADC and DAC on dual core architecture to assure outstanding High sensitivity receiver communication performance with a very high level High linearity transmitter with intelligent of flexibility and programmability for either open gain control standard or fully customized implementations. Fully integrated power line driver Up to 1 Arms, 14 Vpp single ended Configurable active filtering topology Ultra low distortion Embedded temperature sensor Current control 3.3 V or 5 V I/O digital I/O supply Integrated 5 V and 1.8 V linear regulators for AFE and digital core supply 8 V to 18 V line driver power supply October 2011 Doc ID 18349 Rev 1 1/24 www.st.com 24Contents ST7590 Contents 1 Device description 3 2 Pin connection 4 3 Maximum ratings 8 3.1 Absolute maximum ratings . 8 3.2 Thermal data . 8 3.3 Electrical characteristics . 9 4 Analog front end (AFE) 14 4.1 Reception path . 14 4.2 Transmission path 15 4.3 Power amplifier . 15 4.4 Thermal shutdown and temperature control . 15 4.5 Zero-crossing detector . 16 4.6 One time programmable (OTP) memory array . 16 4.7 Power management . 16 4.8 Clock management . 17 5 Application information . 18 6 Package mechanical data 19 7 Revision history . 23 2/24 Doc ID 18349 Rev 1