STA013 STA013B STA013T MPEG 2.5 LAYER III AUDIO DECODER SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) SO28 - Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAM- PLING FREQUENCIES AND THE EXTEN- TQFP44 SION TO MPEG 2.5: 48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMEN- TARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s DIGITAL VOLUME CONTROL DIGITAL BASS & TREBLE CONTROL LFBGA64 SERIAL BITSTREAM INPUT INTERFACE ANCILLARY DATA EXTRACTION VIA I2C IN- TERFACE. ORDERING NUMBERS: STA013 (SO28) 2 SERIAL PCM OUTPUT INTERFACE (I S STA013T (TQFP44) STA013B (LFBGA 8x8) AND OTHER FORMATS) PLL FOR INTERNAL CLOCK AND FOR OUT- PUT PCM CLOCK GENERATION LOW POWER CONSUMPTION: 85mW AT 2.4V DESCRIPTION CRC CHECK AND SYNCHRONISATION ER- The STA013 is a fully integrated high flexibility ROR DETECTION WITH SOFTWARE INDI- MPEG Layer III Audio Decoder, capable of de- CATORS coding Layer III compressed elementary streams, 2 as specified in MPEG 1 and MPEG 2 ISO stand- I C CONTROL BUS ards. The device decodes also elementary streams LOW POWER 3.3V CMOS TECHNOLOGY compressed by using low sampling rates, as speci- 10 MHz, 14.31818 MHz, OR 14.7456 MHz fied by MPEG 2.5. EXTERNAL INPUT CLOCK OR BUILT-IN IN- STA013 receives the input data through a Serial DUSTRY STANDARD XTAL OSCILLATOR Input Interface. The decoded signal is a stereo, DIFFERENT FREQUENCIES MAY BE SUP- mono, or dual channel digital output that can be PORTED UPON REQUEST TO STM sent directly to a D/A converter, by the PCM Out- put Interface. This interface is software program- mable to adapt the STA013 digital output to the APPLICATIONS most common DACs architectures used on the market. PC SOUND CARDS The functional STA013 chip partitioning is de- MULTIMEDIA PLAYERS scribed in Fig.1. February 2004 1/38STA013 - STA013B - STA013T Figure 1. Block Diagram: MPEG 2.5 Layer III Decoder Hardware Partitioning. RESET SDA SCL 26 3 4 2 I C CONTROL 5 9 SDI SDO CHANNEL MPEG 2.5 CONFIG. SERIAL PCM 6 10 LAYER III OUTPUT SCKR INPUT BUFFER PARSER & OUTPUT SCKT DECODER BUFFER VOLUME INTERFACE INTERFACE 7 CORE 11 CONTROL BIT EN LRCKT SYSTEM & AUDIO CLOCKS TEST INTERFACE 8 28 21 201224 25 D98AU965 SRC INT OUT CLK/DATA REQ XTI XTO OCLK TESTEN SCANEN THERMAL DATA Symbol Parameter Value Unit R Thermal resistance Junction to Ambient 85 C/W th j-amb ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V Power Supply -0.3 to 4 V DD V Voltage on Input pins -0.3 to V +0.3 V i DD V Voltage on output pins -0.3 to V +0.3 V O DD T Storage Temperature -40 to +150 C stg T Operative ambient temp -40 to +85 (*) C oper T Operating Junction Temperature -40 to 125 C j (*) guaranteed by design. 2/38