STHV748 Quad 90 V, 2 A, 3/5 levels, high speed ultrasound pulser Datasheet production data Thermal protection Standby function Latch-up free due to HV SOI technology Very few external passive components needed QFN64 9 x 9 x1.0 mm Applications Features Medical ultrasound imaging Pulse waveform generators 0 to 90 V output voltage NDT ultrasound transmission Up to 20 MHz operating frequency Piezoelectric transducer drivers Embedded low-power, floating high-voltage drivers (external voltage rails can be also used) Description Mode operations: 3/5-levels output waveform This monolithic, high-voltage, high-speed pulser 2 A source and sink current generator features four independent channels. It is designed for medical ultrasound imaging Down 20 ps jitter applications, but it can also be used for driving Anti-cross conduction function other piezoelectric, capacitive or MEMS based nd Low 2 harmonic distortion transducers. The STHV748 comprises a Fully integrated clamping-to-ground function controller logic interface circuit, level translators, 8 synchronous active clamp MOSFET gate drivers, noise blocking diodes, and high-power P-channel and N-channel MOSFETs Anti-leakage on output node as the output stage for each channel, clamping- Dedicated half bridge for continuous wave to-ground circuitry, anti-leakage, anti-memory (CW) operations effect block, thermal sensor, and a T/R switch 0.1 W power consumption which guarantees an effective decoupling during 0.6 A source and sink current the transmission phase. Moreover, the STHV748 205 fs RMS jitter 100 Hz-20 kHz includes self-biasing and thermal shutdown blocks. Each channel can support up to five active Fully integrated T/R switch output levels with two half bridges. The output 13.5 on resistance stage of each channel is able to provide 2 A HV MOS topology to minimize current peak output current. In order to reduce power consumption dissipation during continuous wave mode, a Up to 300 MHz BW dedicated half bridge is available and the peak Receiver multiplexing function current is limited to 0.6 A. 2.4 V to 3.6 V CMOS logic interface Table 1. Device summary Auxiliary integrated circuits Order code Package Packaging Noise blocking diodes Fully self-biasing architecture STHV748QTR QFN64 Tape and reel Anti-memory effect for all internal HV nodes January 2016 DocID15450 Rev 5 1/29 This is information on a product in full production. www.st.comContents STHV748 Contents 1 Typical application circuit 3 2 Pin settings 4 2.1 Connection . 4 2.2 Description . 4 2.3 Additional pin description 6 3 Truth table and single channel block description . 8 4 Power-up / Power-down voltage sequence 9 5 Electrical data . 10 5.1 Absolute maximum ratings 10 6 Operating supply voltages and average currents 11 6.1 Digital inputs 11 6.2 Output signals . 12 7 Electrical characteristics 13 8 Timings . 16 9 Oscilloscope acquisitions . 21 9.1 Output phase noise measurement in CW mode . 24 9.1.1 Typical performance characteristics . 24 10 Package information 25 10.1 QFN64 9 x 9 x 1.0 mm 64 pitch 0.50 package information . 25 11 Revision history . 28 2/29 DocID15450 Rev 5