STL7N10F7 N-channel 100 V, 0.027 typ., 7 A STripFET VII DeepGATE Power MOSFET in a PowerFLAT 3.3x3.3 package Datasheet - production data Features Order code V R max I DS DS(on) D STL7N10F7 100 V 0.035 7 A N-channel enhancement mode 1 2 3 Lower R x area vs previous generation DS(on) 4 100% avalanche rated PowerFLAT 3.3x3.3 Applications Switching applications Figure 1. Internal schematic diagram Description th D(5, 6, 7, 8) This device utilizes the 7 generation of design 8 7 6 5 rules of STs proprietary STripFET technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest R in all DS(on) packages. G(4) S(1, 2, 3) 12 3 4 AM15810v1 Table 1. Device summary Order code Marking Package Packaging STL7N10F7 7N10F PowerFLAT 3.3x3.3 Tape and reel April 2014 DocID025972 Rev 2 1/14 This is information on a product in full production. www.st.comContents STL7N10F7 Contents 1 Electrical ratings 3 2 Electrical characteristics . 4 2.1 Electrical characteristics (curves) 6 3 Test circuits 8 4 Package mechanical data . 9 5 Revision history . 13 2/14 DocID025972 Rev 2