STM32L011x3 STM32L011x4 Access line ultra-low-power 32-bit MCU Arm -based Cortex -M0+, up to 16KB Flash, 2KB SRAM, 512B EEPROM, ADC Datasheet - production data Features Ultra-low-power platform 1.65 V to 3.6 V power supply WLCSP25 -40 to 125 C temperature range TSSOP14/20 UFQFPN20 3x3 mm LQFP32 2.133x2.070 mm 169 mils UFQFPN28 4x4 mm 7x7 mm 0.23 A Standby mode (2 wakeup pins) UFQFPN32 5x5 mm 0.29 A Stop mode (16 wakeup lines) 0.54 A Stop mode + RTC + 2 KB RAM Rich Analog peripherals retention 12-bit ADC 1.14 Msps up to 10 channels (down Down to 76 A/MHz in Run mode to 1.65 V) 5 s wakeup time (from Flash memory) 2x ultra-low-power comparators (window mode 41 A 12-bit ADC conversion at 10 ksps and wake up capability, down to 1.65 V) Core: Arm 32-bit Cortex -M0+ 5-channel DMA controller, supporting ADC, SPI, I2C, USART, Timers From 32 kHz to 32 MHz max. 0.95 DMIPS/MHz 4x peripherals communication interface Reset and supply management 1x USART (ISO 7816, IrDA), 1x UART (low power) Ultra-safe, low-power BOR (brownout reset) 1x SPI 16 Mbits/s with 5 selectable thresholds 1x I2C (SMBus/PMBus) Ultralow power POR/PDR Programmable voltage detector (PVD) 7x timers: 1x 16-bit with up to 4 channels, 1x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power Clock sources timer, 1x SysTick, 1x RTC and 2x watchdogs 0 to 32 MHz external clock (independent/window) 32 kHz oscillator for RTC with calibration CRC calculation unit, 96-bit unique ID High speed internal 16 MHz factory-trimmed RC (+/- 1%) All packages are ECOPACK 2 Internal low-power 37 kHz RC Internal multispeed low-power 65 kHz to Table 1. Device summary 4.2 MHz RC Reference Part number PLL for CPU clock Pre-programmed bootloader STM32L011G3, STM32L011K3, STM32L011x3 STM32L011E3, STM32L011F3, USART, SPI supported STM32L011D3 Development support STM32L011G4, STM32L011K4, Serial wire debug supported STM32L011x4 STM32L011E4, STM32L011F4, Up to 28 fast I/Os (23 I/Os 5V tolerant) STM32L011D4 Memories Up to 16 KB Flash memory with ECC 2 KB RAM 512 B of data EEPROM with ECC 20-byte backup register Sector protection against R/W operation September 2017 DocID027973 Rev 5 1/119 This is information on a product in full production. www.st.comContents STM32L011x3/4 Contents 1 Introduction 9 2 Description 10 2.1 Device overview .11 2.2 Ultra-low-power device continuum 13 3 Functional overview 14 3.1 Low-power modes 14 3.2 Interconnect matrix 18 3.3 Arm Cortex-M0+ core . 19 3.4 Reset and supply management 20 3.4.1 Power supply schemes . 20 3.4.2 Power supply supervisor 20 3.4.3 Voltage regulator 21 3.4.4 Boot modes 21 3.5 Clock management . 22 3.6 Low-power real-time clock and backup registers . 24 3.7 General-purpose inputs/outputs (GPIOs) . 24 3.8 Memories . 25 3.9 Direct memory access (DMA) . 25 3.10 Analog-to-digital converter (ADC) 26 3.11 Temperature sensor . 26 3.11.1 Internal voltage reference (V ) . 26 REFINT 3.12 Ultra-low-power comparators and reference voltage 27 3.13 System configuration controller 27 3.14 Timers and watchdogs . 27 3.14.1 General-purpose timers (TIM2, TIM21) . 28 3.14.2 Low-power Timer (LPTIM) . 28 3.14.3 SysTick timer . 28 3.14.4 Independent watchdog (IWDG) . 29 3.14.5 Window watchdog (WWDG) . 29 3.15 Communication interfaces 29 2/119 DocID027973 Rev 5