STM32L100RC Ultra-low-power 32b MCU ARM -based Cortex -M3, 256KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC, memory I/F Datasheet production data Features Ultra-low-power platform LQFP64 (10 10 mm) 1.65 V to 3.6 V power supply -40 C to 105 C temperature range 0.29 A Standby mode (3 wakeup pins) Memories 1.15 A Standby mode + RTC 256 Kbytes of Flash memory with ECC 0.44 A Stop mode (16 wakeup lines) 16 Kbytes of RAM 1.4 A Stop mode + RTC 4 Kbytes of true EEPROM with ECC 8.6 A Low-power run mode 20-byte backup register 185 A/MHz Run mode LCD Driver for up to 8x28 segments 10 nA ultra-low I/O leakage Analog peripherals 8 s wakeup time 12-bit ADC 1Msps up to 20 channels Core: ARM Cortex -M3 32-bit CPU 12-bit DACs 2 channels with output buffers From 32 kHz up to 32 MHz max 2x ultra-low-power-comparators 1.25 DMIPS/MHz (Dhrystone 2.1) (window mode and wakeup capability) Memory protection unit DMA controller 12x channels Reset and supply management 9x peripheral communication interfaces Low-power, ultrasafe BOR (brownout reset) 1x USB 2.0 (internal 48 MHz PLL) with 5 selectable thresholds 3x USARTs Ultra-low-power POR/PDR Up to 8x SPIs (2x I2Ss, 3x 16 Mbits/s) Programmable voltage detector (PVD) 2xI2Cs (SMBus/PMBus) Clock sources 10x timers: 6x 16-bit with up to 4 IC/OC/PWM 1 to 24 MHz crystal oscillator channels, 2x 16-bit basic timers, 2x watchdog 32 kHz oscillator for RTC with calibration timers (independent and window) High Speed Internal 16 MHz CRC calculation unit Internal low-power 37 kHz RC Internal multispeed low-power 65 kHz to 4.2 MHz PLL for CPU clock and USB (48 MHz) Pre-programmed bootloader USB and USART supported Development support Serial wire debug supported JTAG supported 51 fast I/Os (42 I/Os 5V tolerant), all mappable on 16 external interrupt vectors August 2017 DocID024995 Rev 5 1/106 This is information on a product in full production. www.st.comContents STM32L100RC Contents 1 Introduction 8 2 Description . 9 2.1 Device overview 10 2.2 Ultra-low-power device continuum 10 2.2.1 Performance . 11 2.2.2 Shared peripherals 11 2.2.3 Common system strategy 11 2.2.4 Features . 11 3 Functional overview 12 3.1 Low-power modes 13 3.2 ARM Cortex -M3 core with MPU 17 3.3 Reset and supply management 18 3.3.1 Power supply schemes . 18 3.3.2 Power supply supervisor 18 3.3.3 Voltage regulator 19 3.3.4 Boot modes 19 3.4 Clock management . 20 3.5 Low-power real-time clock and backup registers . 22 3.6 GPIOs (general-purpose inputs/outputs) . 22 3.7 Memories . 23 3.8 DMA (direct memory access) 23 3.9 LCD (liquid crystal display) 24 3.10 ADC (analog-to-digital converter) . 24 3.10.1 Internal voltage reference (V ) . 24 REFINT 3.11 DAC (digital-to-analog converter) . 25 3.12 Ultra-low-power comparators and reference voltage 25 3.13 System configuration controller and routing interface . 25 3.14 Timers and watchdogs . 26 3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) 26 3.14.2 Basic timers (TIM6 and TIM7) 27 2/106 DocID024995 Rev 5