Product Information

74HC237D(BJ)

74HC237D(BJ) electronic component of Toshiba

Datasheet
Latches 74HC CMOS logic IC series 6V 16 pins
Manufacturer: Toshiba
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.6885 ea
Line Total: USD 0.69

2665 - Global Stock
Ships to you between
Mon. 20 May to Wed. 22 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
1649 - WHS 1


Ships to you between Mon. 20 May to Wed. 22 May

MOQ : 1
Multiples : 1

Stock Image

74HC237D(BJ)
Toshiba

1 : USD 0.5434
10 : USD 0.4576
100 : USD 0.3417
500 : USD 0.2693
1000 : USD 0.2138
2500 : USD 0.1811
10000 : USD 0.1642
25000 : USD 0.1558
50000 : USD 0.1521

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Type
Logic Family
Quiescent Current
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Package / Case
Packaging
Series
Brand
Mounting Style
Number Of Channels
Number Of Input Lines
Supply Current - Max
Factory Pack Quantity :
Cnhts
Hts Code
Mxhts
Product Type
Subcategory
Taric
LoadingGif

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Additional Infomation About Product

74HC237D CMOS Digital Integrated Circuits Silicon Monolithic 74HC237D74HC237D74HC237D74HC237D 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description 3-to-8 Line Decoder/Latch 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74HC237D is a high speed CMOS 3-to-8 DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs G1 and G2. The 3-bit binary data is stored into the input latch on the high level of GL. The value of this data determines which one of the outputs will go low. When the enable input G1 is held low or G2 is held high, decoding function is inhibited and all the 8 outputs go high. The two enable inputs are provided to ease cascade connection and permits the application address decoder for memory system. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) High speed: t = 12 ns (typ.) at V = 5 V pd CC (2) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (3) Balanced propagation delays: t t PLH PHL (4) Wide operating voltage range: V = 2.0 V to 6.0 V CC(opr) 4. 4. 4. 4. PackagingPackagingPackagingPackaging SOIC16 Start of commercial production 2016-05 2016 Toshiba Corporation 2016-08-04 1 Rev.3.074HC237D 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. 7. 7. IEC Logic SymbolIEC Logic SymbolIEC Logic SymbolIEC Logic Symbol 2016 Toshiba Corporation 2016-08-04 2 Rev.3.0

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Toshiba may also be referenced as

Toshiba Memory
Toshiba Memory Corporation
Toshiba Semiconductor and Storage
TOSHIBA SEMICONDUCTORS
TS4

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