74VHCT574AFT(BE) Toshiba

74VHCT574AFT CMOS Digital Integrated Circuits Silicon Monolithic 74VHCT574AFT74VHCT574AFT74VHCT574AFT74VHCT574AFT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Octal D-Type Flip Flop with 3-State Outputs 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHCT574AFT is an advanced high speed CMOS OCTAL FLIP-FLOP with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CK) and an output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. The input voltage is compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. Note: Output in off-state 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: f = 140MHz (typ.) at V = 5.0 V MAX CC (4) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (5) Compatible with TTL inputs: V = 0.8V (max) IL V = 2.0V (min) IH (6) Power-down protection is provided on all inputs and outputs. (7) Balanced propagation delays: t t PLH PHL (8) Low noise: V = 1.5 V (max) OLP (9) Pin and function compatible with the 74 series (74ACT/HCT/AHCT etc.) 574 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. Start of commercial production 2013-04 2016 Toshiba Corporation 2016-08-04 1 Rev.3.074VHCT574AFT 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP20B 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. MarkingMarking 6. 6. MarkingMarking 2016 Toshiba Corporation 2016-08-04 2 Rev.3.0