TC74VHC299F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC299F, TC74VHC299FT 8-Bit PIPO Shift Register with Asynchronous Clear The TC74VHC299 is an advanced high speed CMOS 8-BIT 2 TC74VHC299F PIPO SHIFT REGISTER fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA) controlled by the two selection inputs (S0, S1). When one or both enable ( G1 , G2 ) are high, the eight I/O are forced to the high-impedance state however, sequential operation or clearing of the register is not affected. TC74VHC299FT All inputs are equipped with protection circuits against static discharge. Features (Note 1) (Note 2) (Note 3) High speed: f = 160 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Balanced propagation delays: t t pLH pHL Weight Wide operating voltage range: V = 2 to 5.5 V CC (opr) SOP20-P-300-1.27A : 0.22 g (typ.) Low noise: V = 1.2 V (max) OLP TSSOP20-P-0044-0.65A : 0.08 g (typ.) Pin and function compatible with 74ALS299 Note 1: Do not apply a signal to A/QA to H/QH bus terminal when it is in the output mode. Damage may result. Note 2: All floating (high impedance) A/QA to H/QH bus terminals must have their input levels fixed by means of pull up or pull down resistors. Note 3: A parasitic diode is formed between A/QA to H/QH bus and V terminals. Therefore bus terminal can not CC be used to interface 5 V to 3 V systems directly. Start of commercial production 1992-10 1 2014-03-01 TC74VHC299F/FT Pin Assignment IEC Logic Symbol (9) SRG 8 CLR R (2) S0 1 20 V CC G1 & 3 EN 13 (3) G2 G1 2 19 S1 (1) 0 S0 0 M (19) 3 S1 1 G 2 3 18 SL (12) CK C4/1/2 G/QG 4 17 QH (11) (8) SR 1, 4D QA (7) A/QA 3, 4D E/QE 5 16 H/QH Z5 5, 13 (13) 3, 4D C/QC 6 15 B/QB F/QF Z6 6, 13 (6) A/QA 7 14 D/QD C/QC (14) D/QD QA 8 13 B/QB (5) E/QE CLR 9 12 CK (15) F/QF GND 10 SR 11 (4) G/QG (16) H/QH 3, 4D (top view) Z12 12, 13 (18) (17) 2, 4D SL QH Truth Table Inputs Inputs Outputs /Outputs Function Mode Output Control Serial Select CLR CK A/QA H/QH QA QH G 1 G 2 S1 S0 SL SR (Note) (Note) Z L H H X X X X X Z Z L L L L X L L X X X L L L L Clear L X L L L X X X L L L L Hold H L L L L X X X QA QH QA QH 0 0 0 0 H L H L L X H H QG H QG n n Shift Right H L H L L X L L QG L QG n n H H L L L H X QB H QB H n n Shift Left H H L L L L X QB L QB L n n Load H H H X X X X a h a h Note: When one or both output controls are high, the eight input/output terminals are in the high-impedance state however sequential or clearing of the register is not affected. Z: High impedance Q : The level of Q before the indicated steady-state input conditions were established. n0 n Q : The level of Q before the most recent active transition indicated by or . nn n a, h: The level of the steady-state inputs A, H, respectively. X: Dont care. 2 2014-03-01