TC74VHC595F(EL,K,F Toshiba

TC74VHC595F/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC595F, TC74VHC595FK 8-Bit Shift Register/Latch (3-state) The TC74VHC595 is an advanced high speed 8-BIT SHIFT TC74VHC595F 2 REGISTER/LATCH fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The TC74VHC595 contains an 8-bit static shift register which feeds an 8- bit storage register. Shift operation is accomplished on the positive going transition of the SCK input. The output register is loaded with the contents of the shift register on the positive going transition of the RCK input. Since RCK and SCK signal are independent, parallel outputs can be held stable during the shift operation. TC74VHC595FK And, since the parallel outputs are 3-state, it can be directly connected to 8- bit bus. This register can be used in serial-to-parallel conversion, data receivers, etc. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Weight Features SOP16-P-300-1.27A : 0.18 g (typ.) VSSOP16-P-0030-0.50 : 0.02 g (typ.) High speed: f = 185 MHz (typ.) at V = 5 V max CC Low power dissipation: ICC = 4 A (max) at Ta = 25C High noise immunity: V = V = 28% V (min) NIH NIL CC Power down protection is provided on all inputs. Balanced propagation delays: tpLH tpHL Wide operating voltage range: V (opr) = 2 V to 5.5 V CC Low noise: V = 1.0 V (max) OLP Pin and function compatible with 74ALS595 Start of commercial production 1992-05 2019 2019-01-31 1 Toshiba Electronic Devices & Storage Corporation TC74VHC595F/FK Pin Assignment IEC Logic Symbol (13) EN3 QB 1 16 V (12) CC RCK C 2 SRG8 QC 2 15 QA (10) R (11) SCK C/1 QD 14 SI 3 QE 4 13 (14) (15) SI 1D 2D 3 QA (1) QB QF 5 12 RCK (2) QC (3) QG 6 11 SCK QD (4) QE QH 7 10 (5) QF (6) QG GND 8 9 QH (7) 2D 3 QH (9) QH (top view) Truth Table Inputs Function SI SCK SCLR RCK G QA thru QH outputs disable X X X X H QA thru QH outputs enable X X X X L Shift register is cleared. X X L X X First stage of S.R. becomes L. Other stages store the data of previous stage, L H X X respectively. First stage of S.R. becomes H. Other stages store the data of previous stage, H H X X respectively. State of S.R. is not changed. X H X X S.R. data is stored into storage register. X X X X Storage register stage is not changed. X X X X X: Dont care 2019 2019-01-31 2 Toshiba Electronic Devices & Storage Corporation