P GND V IN GL C GND VDRV SiC533 www.vishay.com Vishay Siliconix 35 A VRPower Integrated Power Stage DESCRIPTION FEATURES The SiC533 is an integrated power stage solution optimized Thermally enhanced PowerPAK MLP4535-22L for synchronous buck applications to offer high current, high package efficiency, and high power density performance. Packaged Vishays Gen IV MOSFET technology and a in Vishays proprietary 4.5 mm x 3.5 mm MLP package, low-side MOSFET with integrated Schottky SiC533 enables voltage regulator designs to deliver up to diode 35 A continuous current per phase. Delivers up to 35 A continuous current, 40 A at 10 ms peak The internal power MOSFETs utilize Vishays current state-of-the-art Gen IV TrenchFET technology that delivers High efficiency performance industry benchmark performance to significantly reduce High frequency operation up to 2 MHz switching and conduction losses. Power ON reset The SiC533 incorporates an advanced MOSFET gate driver IC that features high current driving capability, adaptive 5 V PWM logic with tri-state and hold-off dead-time control, an integrated bootstrap Schottky diode, Supports PS4 mode light load requirement for IMVP8 with and zero current detection to improve light load efficiency. low shutdown supply current (5 V, 3 A) The driver is also compatible with a wide range of PWM Under voltage lockout for V CIN controllers, supports tri-state PWM, and 5 V PWM logic. Material categorization: for definitions of compliance A user selectable diode emulation mode (ZCD EN ) is please see www.vishay.com/doc 99912 included to improve the light load performance. The device also supports PS4 mode to reduce power consumption APPLICATIONS when system operates in standby state. Multi-phase VRDs for computing, graphics card and memory Intel IMVP-8 VRPower delivery -V , V , V Skylake, Kabylake CORE GRAPHICS SYSTEM AGENT platforms -V for Apollo Lake platforms CCGI Up to 24 V rail input DC/DC VR modules TYPICAL APPLICATION DIAGRAM 5V V IN BOOT PHASE V CIN ZCD EN V SWH V OUT Gate PWM driver PWM controller Fig. 1 - SiC533 Typical Application Diagram S17-1584-Rev. B, 16-Oct-17 Document Number: 75010 1 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 SiC533 www.vishay.com Vishay Siliconix PINOUT CONFIGURATION 11 10 9 8 7 6 25 V 12 5 PHASE SWH V IN 26 P V 13 GND 4 BOOT SWH V 14 3 N.C. SWH 23 C V 15 GND 2 V SWH CIN 24 V 16 1 ZCD EN SWH GL 17 18 19 20 21 22 Fig. 2 - SiC533 Pin Configuration PIN DESCRIPTION PIN NUMBER NAME FUNCTION The ZCD EN pin enables or disables Diode Emulation. When ZCD EN is LOW, diode emulation is allowed. When ZCD EN is HIGH, continuous conduction mode is forced. 1 ZCD EN ZCD EN can also be put in a high impedance mode by floating the pin. If both ZCD EN and PWM are floating, the device shuts down and consumes typically 3 A (9 A max.) current. 2V Supply voltage for internal logic circuitry CIN 23 C Analog ground for the driver IC GND This pin can be either left floating or connected to C . GND P/N P/N Internally it is either connected to GND or not internally LL LL connected depending on manufacturing location. 3N.C. Factory code G on line 3, pin 3 = C G Y W W T Y W W GND Factory code T on line 3, pin 3 = not internally connected 4 BOOT High-side driver bootstrap voltage 5 PHASE Return path of high-side gate driver 6 to 8, 25 V Power stage input voltage. Drain of high-side MOSFET IN 9 to 11, 17, 18, 20, 26 P Power ground GND 12 to 16 V Switch node of the power stage SWH 19, 24 GL Low-side gate signal 21 V Supply voltage for internal gate driver DRV 22 PWM PWM control input ORDERING INFORMATION PART NUMBER PACKAGE MARKING CODE SiC533CD-T1-GE3 PowerPAK MLP4535-22L SiC533 5 V PWM optimized SiC533DB Reference board S17-1584-Rev. B, 16-Oct-17 Document Number: 75010 2 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 P P GND GND P P GND GND P GND GL V P IN GND V V IN DRV V PWM IN